Glossary-9
GLOSSARY
PTS vector
A location in special-purpose memory that holds the
starting address of a PTS control block.
QUAD-WORD
An unsigned, 64-bit variable with values from 0
through 2
64
–1. The QUAD-WORD variable is
supported only as the operand for the EBMOVI
instruction.
quantizing error
An unavoidable A/D conversion error that results
simply from the conversion of a continuous voltage to
its integer digital representation. Quantizing error is
always
±
0.5 LSB and is the only error present in an
ideal A/D converter.
RALU
Register arithmetic-logic unit. A part of the CPU that
consists of the ALU, the PSW, the master PC, the
microcode engine, a loop counter, and six registers.
repeatability error
The variation in code transitions when comparing a
number of actual characteristics from the same
converter on the same channel with the same temper-
ature, voltage, and frequency conditions. The amount
of repeatability error depends on the comparator’s
ability to resolve very similar voltages and the extent
to which random noise contributes to the error.
reserved memory
A memory location that is reserved for factory use or
for future expansion. Do not use a reserved memory
location except to initialize it.
resolution
The number of input voltage levels that an A/D
converter can unambiguously distinguish between.
The number of useful bits of information that the
converter can return.
sample capacitor
A small (2–3 pF) capacitor used in the A/D converter
circuitry to store the input voltage on the selected
input channel.
sample delay
The time period between the time that A/D converter
receives the “start conversion” signal and the time
that the sample capacitor is connected to the selected
channel.
sample delay uncertainty
The variation in the sample delay.
sample time
The period of time that the sample window is open.
(That is, the length of time that the input channel is
actually connected to the sample capacitor.)
Summary of Contents for 87C196CA
Page 9: ...1 Guide to This Manual...
Page 10: ......
Page 13: ...2 Architectural Overview...
Page 14: ......
Page 22: ......
Page 23: ...3 Address Space...
Page 24: ......
Page 33: ...4 Standard and PTS Interrupts...
Page 34: ......
Page 43: ...5 I O Ports...
Page 44: ......
Page 51: ...6 Synchronous Serial I O Port...
Page 52: ......
Page 56: ......
Page 57: ...7 Event Processor Array...
Page 58: ......
Page 65: ...8 J1850 Communications Controller...
Page 66: ......
Page 89: ...9 Minimum Hardware Considerations...
Page 90: ......
Page 93: ...10 Special Operating Modes...
Page 94: ......
Page 98: ......
Page 99: ...11 Programming the Nonvolatile Memory...
Page 100: ......
Page 106: ......
Page 107: ...A Signal Descriptions...
Page 108: ......
Page 118: ......
Page 119: ...Glossary...
Page 120: ......
Page 133: ...Index...
Page 134: ......