Intel 87C196CA, Supplement To User’S Manual

Page: 64 / 136

8XC196L
X SUPPLEMENT
7-6
7.1.3 EPA Interrupt Priority Vector Register
Figure 7-7 illustrates the EPA interrupt priority vector (EPAIPV) register for the 8XC196Lx mi-
crocontroller family.
EPAIPV
Address:
Reset State:
1FA8H
00H
When an EPA
x interrupt occurs, the EPA interrupt priority vector (EPAIPV) register contains a number
that identifies the highest priority, active, multiplexed interrupt source (see Table 7-2).
EPAIPV allows software to branch via the TIJMP instruction to the correct interrupt service routine
when EPA
x is activated. Reading EPAIPV clears the EPA pending bit for the interrupt associated with
the value in EPAIPV. When all the EPA pending bits are cleared, the EPA x pending bit is also cleared.
7 0
— — — PV4 PV3 PV2 PV1 PV0
Bit
Number
Bit
Mnemonic
Function
5:7 — Reserved; for compatibility with future devices, write zeros to these bits.
4:0 PV4:0 Priority Vector
These bits contain a number from 01H to 14H corresponding to the
highest-priority active interrupt source. This value, when used with the
TIJMP instruction, allows software to branch to the correct interrupt
service routine.
Figure 7-7. EPA Interrupt Priority Vector Register (EPAIPV)
Table 7-2. EPA Interrupt Priority Vectors
Value Interrupt Value Interrupt Value Interrupt
14H — 0DH OVR1 06H OVR8
13H — 0CH OVR2 05H OVR9
12H EPA6 0BH OVR3 04H COMP0
†
11H EPA7 0AH — 03H COMP1
†
10H EPA8 09H — 02H OVRTM1
0FH EPA9 08H — 01H OVRTM2
0EH OVR0 07H — 00H None
†
87C196LA, LB only; reserved on 83C196LD.