8XC196L
X SUPPLEMENT
Glossary-6
maskable interrupts
All interrupts except stack overflow, unimplemented
opcode, and software trap. Maskable interrupts can be
disabled (masked) by the individual mask bits in the
interrupt mask registers, and their servicing can be
disabled by the DI (disable interrupt service)
instruction. Each maskable interrupt can be assigned
to the PTS for processing.
monotonic
The property of successive approximation converters
which guarantees that increasing input voltages
produce adjacent codes of increasing value, and that
decreasing input voltages produce adjacent codes of
decreasing value. (In other words, a converter is
monotonic if every code change represents an input
voltage change in the same direction.) Large differ-
ential nonlinearity errors can cause the converter to
exhibit nonmonotonic behavior.
MSB
Most-significant bit of a byte or most-significant byte
of a word.
MSW
Most-significant word of a double-word or quad-
word.
multiplexed bus
The configuration in which the microcontroller uses
both A20:0 and AD15:0 for address and also uses
AD15:0 for data. See also demultiplexed bus.
n-channel FET
A field-effect transistor with an n-type conducting
path (channel).
n-type material
Semiconductor material with introduced impurities
(doping) causing it to have an excess of negatively
charged carriers.
near constants
Constants that can be accessed with nonextended
instructions. Constants in page 00H are near
constants. See also far constants.
near data
Data that can be accessed with nonextended instruc-
tions. Data in page 00H is near data. See also far data.
no missing codes
An A/D converter has no missing codes if, for every
output code, there is a unique input voltage range
which produces that code only. Large differential
nonlinearity errors can cause the converter to miss
codes.
Summary of Contents for 87C196CA
Page 9: ...1 Guide to This Manual...
Page 10: ......
Page 13: ...2 Architectural Overview...
Page 14: ......
Page 22: ......
Page 23: ...3 Address Space...
Page 24: ......
Page 33: ...4 Standard and PTS Interrupts...
Page 34: ......
Page 43: ...5 I O Ports...
Page 44: ......
Page 51: ...6 Synchronous Serial I O Port...
Page 52: ......
Page 56: ......
Page 57: ...7 Event Processor Array...
Page 58: ......
Page 65: ...8 J1850 Communications Controller...
Page 66: ......
Page 89: ...9 Minimum Hardware Considerations...
Page 90: ......
Page 93: ...10 Special Operating Modes...
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Page 98: ......
Page 99: ...11 Programming the Nonvolatile Memory...
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Page 106: ......
Page 107: ...A Signal Descriptions...
Page 108: ......
Page 118: ......
Page 119: ...Glossary...
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Page 133: ...Index...
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