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Glossary-7
GLOSSARY
nonlinearity
The maximum deviation of code transitions of the
terminal-based characteristic from the corre-
sponding code transitions of the ideal characteristic.
nonmaskable interrupts
Interrupts that cannot be masked (disabled) and
cannot be assigned to the PTS for processing. The
nonmaskable interrupts are stack overflow, unimple-
mented opcode, software trap, and NMI. The DI
(disable interrupt service) and EI (enable interrupt
service) instructions have no effect on nonmaskable
interrupts.
npn transistor
A transistor consisting of one part p-type material and
two parts n-type material.
off-isolation
The ability of an A/D converter to reject (isolate) the
signal on a deselected (off) output.
p-channel FET
A field-effect transistor with a p-type conducting
path.
p-type material
Semiconductor material with introduced impurities
(doping) causing it to have an excess of positively
charged carriers.
PC
Program counter.
phase-locked loop
A component of the clock generation circuitry. The
phase-locked loop (PLL) and the input pin (PLLEN)
combine to enable the microcontroller to attain its
maximum operating frequency with an external clock
whose frequency is either equal to or one-half that
maximum frequency or with an external oscillator
whose frequency is one-half that maximum
frequency.
PIC
Programmable interrupt controller. The module
responsible for handling interrupts that are to be
serviced by interrupt service routines that you
provide. Also called simply the interrupt controller.
PIH
Peripheral interrupt handler. An integrated module
that provides interrupt vectors for specific EPA
interrupt requests to the interrupt controller or PTS.
PLL
See phase-locked loop.
Summary of Contents for 87C196CA
Page 9: ...1 Guide to This Manual...
Page 10: ......
Page 13: ...2 Architectural Overview...
Page 14: ......
Page 22: ......
Page 23: ...3 Address Space...
Page 24: ......
Page 33: ...4 Standard and PTS Interrupts...
Page 34: ......
Page 43: ...5 I O Ports...
Page 44: ......
Page 51: ...6 Synchronous Serial I O Port...
Page 52: ......
Page 56: ......
Page 57: ...7 Event Processor Array...
Page 58: ......
Page 65: ...8 J1850 Communications Controller...
Page 66: ......
Page 89: ...9 Minimum Hardware Considerations...
Page 90: ......
Page 93: ...10 Special Operating Modes...
Page 94: ......
Page 98: ......
Page 99: ...11 Programming the Nonvolatile Memory...
Page 100: ......
Page 106: ......
Page 107: ...A Signal Descriptions...
Page 108: ......
Page 118: ......
Page 119: ...Glossary...
Page 120: ......
Page 133: ...Index...
Page 134: ......