Intel 87C196CA, Supplement To User’S Manual

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8-1
CHAPTER 8
J1850 COMMUNICATIONS CONTROLLER
The J1850 communications controller manages communications between multiple network
nodes. This integrated peripheral supports the 10.4 Kb/s VPW (variable pulse width) medium-
speed class B in-vehicle network protocol. It also supports both the standard and in-frame re-
sponse (IFR) message framing as specified by the Society of Automotive Engineering (SAE)
J1850 (revised May 1994) technical standards. Its lower cost per node makes it suitable for diag-
nostics and non-real-time data sharing in applications with high numbers of nodes. This chapter
details the integrated J1850 controller and explains how to configure it.
8.1 J1850 FUNCTIONAL OVERVIEW
The integrated J1850 communications controller transfers messages between network nodes ac-
cording to the J1850 protocol. The complete J1850 communications protocol solution includes
an on-chip, J1850 digital-logic controller working with an external analog bus transceiver circuit.
Figure 8-1 illustrates the J1850 protocol with the J1850 controller integrated on the 87C196LB
16-bit microcontroller and a standalone J1850 bus transceiver device. The example uses the Har-
ris HIP7020 as the remote transceiver device.
Figure 8-1. Integrated J1850 Communications Protocol Solution
The benefit of an integrated, J1850 protocol solution is threefold:
•
Minimizes CPU overhead for reception and transmission of J1850 messages.
•
Frees up serial and parallel communications ports for other purposes.
•
Offers significant printed-circuit board area savings when compared with conventional
standalone protocol devices.
A5168-01
87C196LB
Microcontroller
PLL/
CLKOUT
Clock
TXJ1850
RXJ1850
TX
RX
HIP7020
J1850
Bus