Intel 87C196CA, Supplement To User’S Manual

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8XC196L
X SUPPLEMENT
8-16
If a third byte is received before J_RX is read, a J1850ST core interrupt is generated and the
OVR_UNDR (J_STAT.3) bit records a receiver overrun error in the J_STAT register.
8.5.3 IFR Messages
In-frame response (IFR) messaging is identical in setup to standard messaging for both transmis-
sion and reception. It uses the same registers to configure, communicate, and control data. The
difference is that the requestor initiating the IFR message sequence writes the message specifying
a response from either one or more nodes in the system. Framing a message in this manner by-
passes needless CPU overhead that can result from lengthy EOF symbols, and it gives you a faster
response to the information you are accessing from remote sites in your system. (Refer to “In-
frame Response Messaging” on page 8-12 for a detailed explanation).
8.6 PROGRAMMING THE J1850 CONTROLLER
This section explains how to configure the J1850 controller. Several registers combine to control
the configuration: the command register, the configuration register, the delay compensation reg-
ister, and the status register.
Programming the J1850 controller requires that you first program the configuration and delay
registers during initialization. You need to program these two registers only once per initializa-
tion sequence.
After initialization, you must first program the command register, followed by either the receive
or transmit register, and then the status register.
8.6.1 Programming the J1850 Command (J_CMD) Register
The J1850 command register (Figure 8-16) determines the messaging type, specifies the number
of bytes to be transmitted in the next message frame, and updates the status of the message trans-
mission in progress.