5-3
I/O PORTS
Figure 5-1. Ports 1, 2, 5, and 6 Internal Structure (87C196LA, LB Only)
5.2.1
Configuring Ports 1, 2, 5, and 6 (Bidirectional Ports)
Using the port mode register, you can individually configure each pin for port 1, 2, 5, and 6 to
operate either as a general-purpose I/O signal (I/O mode) or as a special-function signal (special-
function mode). In either mode, three configurations are possible: complementary output, high-
Q2
Q1
P
x
_MODE
P
x
_DRV
SFDIR
0
1
P
x
_REG
Sample
Latch
PH1 Clock
Internal Bus
SFDATA
Any Write to P
x
_MODE
Q
R
Weak
Pullup
RESET#
Q3
Q4
Buffer
Read Port
S
300ns Delay
I/O Pin
RESET#
A5265-01
150
Ω
to 200
Ω
R1
0
1
V
SS
Medium
Pullup
V
SS
V
SS
V
CC
RESET#
P
x
_PIN
D
Q
LE
Summary of Contents for 87C196CA
Page 9: ...1 Guide to This Manual...
Page 10: ......
Page 13: ...2 Architectural Overview...
Page 14: ......
Page 22: ......
Page 23: ...3 Address Space...
Page 24: ......
Page 33: ...4 Standard and PTS Interrupts...
Page 34: ......
Page 43: ...5 I O Ports...
Page 44: ......
Page 51: ...6 Synchronous Serial I O Port...
Page 52: ......
Page 56: ......
Page 57: ...7 Event Processor Array...
Page 58: ......
Page 65: ...8 J1850 Communications Controller...
Page 66: ......
Page 89: ...9 Minimum Hardware Considerations...
Page 90: ......
Page 93: ...10 Special Operating Modes...
Page 94: ......
Page 98: ......
Page 99: ...11 Programming the Nonvolatile Memory...
Page 100: ......
Page 106: ......
Page 107: ...A Signal Descriptions...
Page 108: ......
Page 118: ......
Page 119: ...Glossary...
Page 120: ......
Page 133: ...Index...
Page 134: ......