IDT Tsi310TM, User Manual

Page: 204 / 207

Index 204
Tsi310 User Manual
80B6020_MA001_05
L
Latency Timer Register 79
lead-free package 201
Lower Memory Base Address Register 81
M
mechanical information 197
Memory Base Register 92
Memory Limit Register 93
Miscellaneous Control Register 111
Miscellaneous Control Register 2 148
N
Next Capabilities Pointer Register 134
,
142
O
opaque address range 25
Opaque Memory Base Register 129
Opaque Memory Base Upper 32 Bits Register 131
Opaque Memory Enable Register 128
Opaque Memory Limit Register 130
Opaque Memory Limit Upper 32 Bits Register 132
OPAQUE_EN signal 157
operating conditions
AC 193
DC 193
optional base address register 55
ordering information 201
ordering rules
pci 61
pci-x 60
P
P_ACK64# signal 151
P_AD signal 151
P_C/BE signal 151
P_CFG_BUSY signal 158
P_CLK signal 151
P_DEVSEL signal 152
P_DRVR_MODE signal 158
P_FRAME# signal 152
P_GNT# signal 152
P_IDSEL signal 152
P_IRDY# signal 152
P_LOCK# signal 152
P_PAR signal 152
P_PAR64 signal 152
P_PERR# signal 153
P_REQ# signal 153
P_REQ64# signal 153
P_RST# signal 153
P_SERR# signal 153
P_STOP# signal 153
P_TRDY# signal 153
P_VDDA signal 161
package characteristics 197
package diagram 198
packaging information 197
parity error 55
parity errors 55
PCI buffers 24
PCI transactions 28
PCI-to-PCI Bridge Support Extensions Register 145
PCI-X Bridge Status Register 137
PCI-X ID Register 133
PCI-X Secondary Status Register 135
PCI-X transactions 29
phase locked loop 45
pinout 163
PLL 45
primary interface 47
secondary interface 48
power dissipation 194
power management 54
Power Management Capabilities Register 143
Power Management Control/Status Register 144
power management events 54
Power Management ID Register 142
Prefetchable Base Upper 32 Bits Register 96
Prefetchable Limit Upper 32 Bits Register 97
Prefetchable Memory Base Register 94
Prefetchable Memory Limit Register 95
Primary Bus Downstream Split Transaction Register 141
Primary Bus Number Register 84
Primary Data Buffering Control Register 105
Primary Retry Counter Register 121
product code 201
R
read transactions
configuration read 35
general 33
I/O read 35
memory read 33
non-prefetchable and dword read 35
prefetchable reads 36
recommended DC operating conditions 193
register map 65
registers 63
related documentation 17
RESERVED2 signal 158
reset options