IDT Tsi310TM, User Manual

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6. Signals and Pinout 155
Tsi310 User Manual
80B6020_MA001_05
S_IRDY# I/O 1 Initiator Ready: This signal indicates the ability of the initiator on the
secondary bus to complete the current data phase of the transaction.
It is used in conjunction with S_TRDY#.
S_IRDY# is driven by the bridge when performing a secondary bus
transaction on behalf of a primary bus master.
S_IRDY# is monitored by the bridge when a secondary bus master is
performing a transaction on the secondary bus through the bridge.
S_LOCK# I/O 1 Lock: Indicates that an atomic (unbroken) operation is required that
may need multiple secondary bus transactions to complete.
The bridge drives S_LOCK# only to propagate an exclusive access
from the primary bus to the secondary bus and monitors S_LOCK# as
part of that protocol.
When acting as a target on the secondary interface, the bridge
ignores S_LOCK#.
S_PAR I/O 1 Parity: Parity protection bit for the lower half of the address/data and
command/byte enable buses on the secondary interface. It provides
even parity across S_AD(31:00) and S_C/BE(3:0)#.
S_PAR64 I/O 1 Parity Upper DWord: Parity protection bit for the upper half of the
address/data and command/byte enable buses on the secondary
interface. It provides even parity across S_AD(63:32) and
S_C/BE(7:4)#.
S_PERR# I/O 1 Parity Error: Used to report data parity errors on the secondary
interface.
S_PERR# is monitored by the bridge when performing a secondary
bus write transaction on behalf of a primary bus master or when
serving as the selected slave for a secondary bus read transaction.
S_PERR# is driven by the bridge when performing a secondary bus
read transaction on behalf of a primary bus master or when serving as
the selected slave during a secondary bus write transaction.
S_REQ1GNT# I 1 Request 1: This is a dual-purpose signal:
• When the Tsi310 internal arbiter is enabled, this signal is used as a
request input, to be activated by a secondary bus master requesting
the use of the secondary bus.
• When the Tsi310 internal arbiter is disabled, this signal is used by
the bridge as its grant input signal.
S_REQ2# - S_REQ6# I 5 Requests 2-6: Activated by the secondary bus masters to request the
use of the secondary bus.
S_REQ64# I/O 1 Request 64-Bit Transfer: This signal, when asserted by the current
master on the secondary bus, indicates a desire to transfer data using
64 bits.
Table 14: Secondary Interface Signals (Continued)
Signal Name I/O Width Description