IDT Tsi310TM, User Manual, Page: 49 / 207

3. Clocking and Reset Options 49
Tsi310 User Manual
80B6020_MA001_05
The Tsi310 is expecting at most one transition on the S_CLK_STABLE input from the not
stable to the stable state. The S_CLK_STABLE input may also be tied-up if the secondary clock
input will always be stable prior to the de-assertion of the primary bus reset signal or the
secondary bus reset bit of the bridge control register (see
Section 3.6.2 on page 51 ).There are
several possibilities for the source of the S_CLK_STABLE input signal. For example: some
clock generation circuits that use phase-locked loops provide a lock indicator that may be used
for this purpose. Care must be taken to assure that the lock indicator does not toggle randomly
while the PLL is locking to the desired frequency before reaching a steady state. Another
possibility is to tie-up the signal, this may be useful for fixed frequency applications with simple
clock generators or oscillators. A third possibility may be to use a ‘power good’ indicator, if the
proper stability assurances can be made. Other ways to provide the S_CLK_STABLE input
signal may also be possible.
The S_CLK_STABLE input provides another measure of control for cases where the secondary
bus mode and clock frequency could vary from reset to reset, as in motherboard applications
with pluggable slots. In these applications the external clock generation circuitry will need to
adapt to the changes along with the Tsi310. If the S_CLK_STABLE signal is initially held low
during reset, the bridge will not control the S_PCIXCAP network and the clock generation
circuitry is free to do its own mode and frequency determination sequence. The clock frequency
may be adjusted based on the number of populated slots, determined by the PRSNT pins of the
bus. Once the frequency of the S_CLK input is stable, the clock circuit can assert the
S_CLK_STABLE signal to allow the bridge to complete the reset sequence. The clock
generation circuitry must ensure that the clock frequency it provides falls within the range that
the bridge will determine and broadcast on the initialization pattern. To do this, the clock
generator may need to drive the proper values on the S_SEL100 and S_PCIXCAP inputs, in
addition to controlling the S_CLK_STABLE signal. A mismatch between the broadcast
initialization pattern and the actual operating mode and frequency of the bus is a violation of the
architecture and will cause unpredictable results.
3.5 Driver Impedance Selection
On the Tsi310, the output drivers for the bussed PCI/PCI-X interface signals are capable of two
different output impedances, a 40 ohm output impedance for point-to-point applications and a
20 ohm output impedance for multi-point configurations. The output impedance for the primary
and secondary interfaces is separately controlled. The Tsi310 selects a default impedance value
at the de-assertion of the bus reset on the basis of the bus mode and frequency initialization
pattern which was received on the primary interface or generated on the secondary interface. It
is assumed that if a bus is configured to be in the PCI-X 133 mode, it will be lightly loaded and
therefore have a higher impedance. The drivers are put into point-to-point mode for this case.
For all other PCI-X and all PCI configurations, the bridge assumes that the bus is more heavily
loaded and has a lower impedance, so the drivers are set to multi-point mode.