IDT Tsi310TM, User Manual

Page: 51 / 207

3. Clocking and Reset Options 51
Tsi310 User Manual
80B6020_MA001_05
On the de-assertion or rising edge of the P_RST# signal, the initialization pattern is received off
of the bus and latched into the bridge. If the indication is that the primary bus is operating in
PCI-X mode, an internal PLL sources the clock tree for the primary clock domain. The
appropriate range and tuning bits for the PLL are set according to the indicated frequency range,
and an internal PLL reset signal is deactivated to allow the PLL to begin locking to the P_CLK
input frequency. Since the PLL requires an allowance of 100

s to accomplish this frequency
lock, an internal reset is held on the logic in the primary clock domain until this time period has
elapsed. While the internal logic reset is active, the bridge will not respond to any primary bus
transactions. When the primary bus is operating in PCI mode, the internal PLL for the primary
interface is not used. In this case, the internal PLL reset remains activated, keeping the PLL in
the bypass mode, and the internal logic reset is held for only seven additional primary clock
cycles after the rising edge of P_RST#.
3.6.2 Secondary Reset
The bus reset for the secondary interface is called S_RST#, it is an output from the Tsi310.
Whenever P_RST# is asserted or when the secondary bus reset bit (bit 6) of the bridge control
register is set to b’1’, S_RST# is asserted immediately, asychronously to the secondary bus
clock. When the secondary bus reset bit is being used to control S_RST#, the software must be
sure that the required minimum reset active time (T
rst
) of 1 ms is met.
Several things must occur at or prior to the de-assertion of the secondary bus reset signal. Once
P_RST# is de-asserted or the secondary bus reset bit is changed from b’1’ to b’0’, indicating
that S_RST# should be deactivated, the Tsi310 will wait for the S_CLK_STABLE signal to be
asserted before proceeding. The S_CLK input must be stable at a frequency within the bus
capability limits prior to the assertion of S_CLK_STABLE. Since the
PCI Local Bus
Specification (Revision 2.2) requires that the bus clock be stable for at least 100

s prior to the
de-assertion of the bus reset, S_CLK_STABLE serves as a gate to a timer that ensures that this
requirement is met. During this time delay period, the determination of the secondary bus mode
and frequency capability is made through the use of the programmable pull-up circuit described
in
Section 3.3.2 on page 47 . This process may include up to 80

s for the capacitive load on the
S_PCIXCAP net to be charged, making it prudent to overlap the two functions. By the time the
100

s timer expires, the bus capability will have been determined and the appropriate
initialization pattern can be driven on the secondary interface. The S_RST# signal is then
de-asserted a minimum of ten secondary bus cycles later.