IDT Tsi310TM, User Manual

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5. Configuration Registers 132
Tsi310 User Manual
80B6020_MA001_05
5.5.16 Opaque Memory Limit Upper 32 Bits Register
This register specifies upper address bits 63:32 of the opaque memory address range. It is used
in conjunction with the opaque memory base register, the opaque memory limit register, and the
opaque memory base upper 32 bits register to specify a range of 64-bit addresses that are used
exclusively on the secondary bus. These memory addresses will not be accepted by the bridge
on the primary or the secondary buses. This address range is enabled by bit 0 of the Opaque
Memory Enable register.
Address Offset x‘7C’
Access Read/Write
Reset Value x‘FFFF FFFF’
Opaque Memory Limit Upper 32 Bits
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit(s) Access Field Name and Description
31:0 RW Opaque Memory Limit Upper 32 Bits
Address bits 63:32 of the limit address for the opaque memory address range. Memory
operations in this range are not accepted by the bridge on either the primary or secondary
interfaces.