IDT Tsi310TM, User Manual

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6. Signals and Pinout 157
Tsi310 User Manual
80B6020_MA001_05
6.4 Strapping Pins and Other Signals
Table 15: Strapping Pins and Other Signals
Signal Name
a
I/O Width Description
64_BIT_DEVICE# I 1 Physical bus width of the PCI-X device: Used only when the Tsi310 is
employed as the bus interface on a PCI-X add-in card. The
PCI-X
Specification requires that such devices indicate the physical width of
their bus in bit 16 of the PCI-X bridge status register. Bit 16 of the
PCI-X bridge status register is set directly from the inverse of the
64_BIT_DEVICE# pin. This information is used solely by the
configuration software; operation of the Tsi310 is unaffected.
0 = Bit 16 of the PCI-X bridge status register is set to b’1’, indicating a
64 bit bus.
1 = Bit 16 of the PCI-X bridge status register is set to b’0’, indicating a
32 bit bus.
BAR_EN I 1 Base Address Register Enable: Used to enable the base address
register at reset or power up. The 64-bit register located at offsets
x'10' and x'14' claims a 1 MB memory region when enabled. The
register returns all zeroes to read accesses and the associated
memory region is not claimed when disabled.
0 = BAR disabled, register reads returns 0’s, no memory region
claimed.
1 = BAR enabled, bits 63:20 can be written by software to claim a 1
MB memory region.
IDSEL_REROUTE_
EN
I 1 IDSEL Reroute Enable: Used to enable the IDSEL reroute function at
reset or power up. The reset value of the secondary bus private
device mask register is modified according to the tie value of the
IDSEL_REROUTE_EN pin. Note that configuration software can
subsequently modify the secondary bus private device mask register,
regardless of how the IDSEL_REROUTE_EN pin is tied.
0 = Reset value of the secondary bus private device mask register is
x’00000000’.
1 = Reset value of the secondary bus private device mask register is
x’22F20000’.
OPAQUE_EN I 1 Opaque Region Enable: Used to enable the opaque memory region
at reset or power up. The reset value of bit 0 of the opaque memory
enable register is modified according to the tie value of the
OPAQUE_EN pin. The configuration software can subsequently
modify bit 0 of the opaque memory enable register, regardless of how
the OPAQUE_EN pin is tied.
0 = Reset value of bit 0 of the opaque memory enable register is b’0’.
1 = Reset value of bit 0 of the opaque memory enable register is b’1’.