IDT Tsi310TM, User Manual, Page: 69 / 207

5. Configuration Registers 69
Tsi310 User Manual
80B6020_MA001_05
Prefetchable Base Upper 32 Bits x‘28’ Base of prefetchable address range bits 63:32 96
Prefetchable Limit Upper 32 Bits x‘2C’ Upper limit of prefetchable address range bits 63:32 97
I/O Base Upper 16 Bits x‘30’ Base of I/O address range bits 63:32 98
I/O Limit Upper 16 Bits x‘32’ Upper limit of I/O address range bits 63:32 99
Capabilities Pointer x‘34’ Specifies a pointer to a capabilities list item 100
Reserved Registers x‘35’ Reserved 100
Interrupt Line x‘3C’ Communicates interrupt line routing information between
initialization code and device driver 101
Interrupt Pin x‘3D’ not supported 101
Bridge Control x‘3E’ Provides bridge-specific Command register extensions 102
Device-Specific Configuration Space Registers
Primary Data Buffering Control x‘40’ Provides controls for primary bus memory operations 105
Secondary Data Buffering
Control x‘42’ Provides controls for secondary bus memory operations 108
Miscellaneous Control x‘44’ Controls miscellaneous functions, such as parity error
operations 111
Arbiter Mode x‘50’ Controls secondary bus arbitration logic 113
Arbiter Enable x‘54’ Enables arbitration for requestors of internal secondary
bus arbitration logic 115
Arbiter Priority x‘58’ Indicates whether high or low priority is assigned to internal
secondary bus arbitration logic requests 117
SERR# Disable x‘5C’ Controls assertion of SERR# on primary bus 119
Primary Retry Counter x‘60’ Defines number of primary bus retries 121
Secondary Retry Counter x‘64’ Defines number of secondary bus retries 123
Discard Timer Control x‘68’ Controls duration and enabling of discard timer 125
Retry and Timer Status x‘6C’ Indicates expiration of a retry counter or discard timer 127
Opaque Memory Enable x‘70’ Enables all opaque memory registers 128
Opaque Memory Base x‘74’ Specifies base of opaque memory address range (bits
31:20) 129
Table 12: Register Summary (Continued)
Register Name
Starting
Address Description See Page