IDT Tsi310TM, User Manual

Page: 113 / 207

5. Configuration Registers 113
Tsi310 User Manual
80B6020_MA001_05
5.5.4 Arbiter Mode Register
This register provides controls for the secondary bus arbitration logic on the bridge.
Address Offset x‘50’
Access See bit descriptions.
Reset Value x’0800’ When S_INT_ARB_EN# (pin T21) is tied low. For
more information on strapping considerations, see
Section 6.4
on page 157 .
Reset Value x’0801’ When S_INT_ARB_EN# (pin T21) is tied high. For
more information on strapping considerations, see
Section 6.4
on page 157 .
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15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit(s) Access Field Name and Description
15:8 RW Arbiter Fairness Counter
This is the initialization value of a counter used by the internal arbiter. It controls the number of
PCI bus cycles that the arbiter holds a device’s PCI bus grant active after detecting a PCI bus
request from another device. The counter is reloaded whenever a new PCI bus grant is
asserted. For every new PCI bus grant, the counter is armed to decrement when it detects the
new fall of FRAME#. If the arbiter fairness counter is set to x‘00’, the arbiter will not remove a
device’s PCI bus grant until the device has deasserted its PCI bus request.
The reset value is x‘08’.
7:2 RO Reserved