IDT Tsi310TM, User Manual

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5. Configuration Registers 119
Tsi310 User Manual
80B6020_MA001_05
5.5.7 SERR# Disable Register
This register controls the assertion of the SERR# signal on the primary bus due to certain errors.
Address Offset x‘5C’
Access Read/Write
Reset Value x‘00’
Reserved PERR# on Posted W
rite
s
SERR#
Di
sable
Pri
m
ary
Di
sca
rd time
r SERR# Di
sa
ble
Second
ary D
iscard
ti
me
r SERR#
Di
sable
Pri
m
ary
Re
try Coun
t SERR# Di
sa
ble
Second
ary R
e
try
Cou
n
t SERR#
Di
sable
7 6 5 4 3 2 1 0
Bit(s) Access Field Name and Description
7:5 RO Reserved
4 RW PERR# on Posted Writes SERR# Disable
Controls the SERR# assertion when a PERR# is detected on the destination bus on an error
free posted write.
0 = Assert SERR# and set bit 14 of the status register if the SERR# enable bit 8 in the
command register is set. Discard the delayed transaction.
1 = Disable the assertion of SERR#.
3 RW Primary Discard Timer SERR# Disable
Controls the SERR# assertion when the primary discard timer has expired.
0 = Assert SERR# and update status bit 14 in the status register if the primary discard timer
expires, the SERR# enable bit 8 in the Command register is set, and bit 11 of the bridge control
register is set. Discard the delayed transaction and set bit 3 of the retry and timer status
register.
1 = Disable the assertion of SERR# if the primary discard timer expires. Discard the delayed
transaction and set bit 3 of the retry and timer status register.