IDT Tsi310TM, User Manual

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Tsi310 User Manual
80B6020_MA001_05
3. Clocking and Reset Options
This chapter discusses the following topics:
• “Clocking Domains” on page 45
• “Clock Jitter” on page 46
• “Mode and Clock Frequency Determination” on page 46
• “Clock Stability” on page 48
• “Driver Impedance Selection” on page 49
• “Reset Functions and Operations” on page 50
• “Bus Parking and Bus Width Determination” on page 53
• “Power Management and Hot-Plug” on page 54
• “Secondary Device Masking” on page 55
• “Handling of Address Phase Parity Errors” on page 55
• “Optional Base Address Register” on page 55
• “Optional Configuration Register Access from the Secondary Bus” on page 56
• “Short Term Caching” on page 57
3.1 Clocking Domains
The Tsi310 has two clocking domains, one for the primary interface and one for the secondary
interface. Each interface has its own clock input pin. The primary interface is controlled by the
P_CLK input. The secondary interface and the internal arbiter are controlled by the S_CLK
input. The Tsi310 does not supply the clocks on either interface. The two bus clocks may be run
synchronously or asynchronously to one another. The two clock frequencies are independent of
each other and each may have any value allowed by the PCI/PCI-X bus architectures. A spread
spectrum clock input is supported for either or both interfaces within the architectural bounds.
The Tsi310 contains a separate internal phase-locked loop (PLL) circuit for each clocking
domain. The PLL for each interface is employed when its bus is running in PCI-X mode, as
determined by the bus initialization process described below. When either bus is running in PCI
mode, the respective PLL is bypassed to allow for any clock frequency from zero to 66 MHz.