3. Clocking and Reset Options
46
Tsi310 User Manual
80B6020_MA001_05
3.2
Clock Jitter
Clock jitter is defined as the relationship of one clock edge to a subsequent clock edge,
measured at the same point. If these two edges are separated by one clock cycle, it is called
cycle-to-cycle or short-term jitter. If they are separated by hundreds or thousands of cycles, it is
called long-term jitter. As specified in
, the Tsi310 tolerates a maximum
of ± 250 ps of short-term and long-term jitter on each of its clock inputs. Clock jitter introduced
by the internal PLLs of the bridge is accounted for within this maximum specification.
Careful design of the clock generation circuitry is an important factor in determining the speed
of the bus. As indicated in the PCI and PCI-X architectures, all sources of clock jitter must be
considered when determining the bus clock frequency. The minimum and maximum clock
period specifications must not be violated for any single clock cycle. The system clock output
period, including all sources of clock period variation such as jitter and component tolerances,
must always be within the minimum and maximum limits defined for the mode in which the bus
is configured. For example, if a specific system clock design has a maximum clock period
variation of 180 ps, then the nominal clock period for the PCI-X 133 range needs to be at least
7.68ns (7.5ns + 0.180ns), making the maximum frequency allowed for this case is just over 130
MHz.
3.3
Mode and Clock Frequency Determination
As explained in Sections 6.2 and 8.9 of the
PCI-X Addendum to PCI Local Bus Specification
(Revision 1.0a)
, the mode and frequency range of each bus is determined by the values on its
M66EN and PCIXCAP signals when the bus reset signal is active. Each bus client is then
informed of the determination through an initialization pattern that is broadcast at the
de-assertion or rising edge of the reset signal. This process is accomplished on the secondary
interface differently than on the primary interface, due to architectural requirements for PCI-X
bridges. The differences for each interface are discussed in the following sections.
3.3.1
Primary Interface
The primary interface is capable of operating in either the conventional PCI mode or in PCI-X
mode, at any of the defined frequency ranges. When the Tsi310 is used on an add-in card, the
M66EN and PCIXCAP pins on the card edge connector should be left unconnected (except for a
required decoupling capacitor to provide an AC return path) to indicate this maximum
capability. As defined by Section 9.10 of the
PCI-X Addendum to PCI Local Bus Specification
(Revision 1.0a)
, an add-in card’s PCIXCAP pin must be consistent with the 133 MHz Capable
bit in the PCI-X Bridge Status register. When the Tsi310 is used on a motherboard, the system
designer should wire the M66EN and PCIXCAP signal networks to all clients on the bus in the
architected fashion to achieve the desired results.
Summary of Contents for Tsi310TM
Page 8: ...Contents 8 Tsi310 User Manual 80B6020_MA001_05...
Page 10: ...List of Figures 10 Tsi310 User Manual 80B6020_MA001_05...
Page 12: ...List of Tables 12 Tsi310 User Manual 80B6020_MA001_05...
Page 18: ...18 Tsi310 User Manual 80B6020_MA001_05...
Page 44: ...2 Bus Operation 44 Tsi310 User Manual 80B6020_MA001_05...
Page 58: ...3 Clocking and Reset Options 58 Tsi310 User Manual 80B6020_MA001_05...
Page 62: ...4 Transaction Ordering 62 Tsi310 User Manual 80B6020_MA001_05...
Page 150: ...5 Configuration Registers 150 Tsi310 User Manual 80B6020_MA001_05...
Page 170: ...6 Signals and Pinout 170 Tsi310 User Manual 80B6020_MA001_05...
Page 190: ...7 JTAG Boundary Scan 190 Tsi310 User Manual 80B6020_MA001_05...
Page 196: ...8 Electrical Characteristics 196 Tsi310 User Manual 80B6020_MA001_05...
Page 200: ...9 Package Information 200 Tsi310 User Manual 80B6020_MA001_05...
Page 202: ...A Ordering Information 202 Tsi310 User Manual 80B6020_MA001_05...
Page 206: ...Index 206 Tsi310 User Manual 80B6020_MA001_05...