3. Clocking and Reset Options
57
Tsi310 User Manual
80B6020_MA001_05
3.13
Short Term Caching
Short Term Caching was developed to provide performance improvements where upstream
devices are not able to stream data continuously to meet the prefetching needs of the Tsi310. As
defined in the
PCI-to-PCI Bridge Architecture Specification (Revision 2.0)
, when the master
completes the transaction, the bridge is required to discard the balance of any data that was
prefetched for the master. To prevent performance impacts when dealing with target devices that
can only stream data of from 128 to 512 bytes before disconnecting, the Tsi310 has a feature
called “Short Term Caching”. This feature applies only when the secondary bus is operating in
PCI mode and provides a time limited read data cache in which the bridge will not discard
prefetched read data after the request has been completed on the initiating bus.
Short Term Caching is an optional feature which is enabled by setting the “Miscellaneous
Control Register 2” bits 8 and 15. When enabled, the Tsi310 will not discard the additional
prefetched data when the read transaction has been completed on the initiating bus. As such, the
Tsi310 will continue to prefetch data up to the amount specified by the “Secondary Data
Buffering Control Register” offset x’42’ bits 14:12. Should the initiator generate a new
transaction requesting the previously prefetched data, the Tsi310 will return that data. However,
the Tsi310 will discard the data approximately 64 secondary bus side clocks after some of the
data for a request has been returned to the initiator, and the initiator has not requested additional
data.
If this feature is enabled, it will apply to all devices attached to the secondary side of the Tsi310.
System designers need to ensure that all attached devices have memory region(s) that are
architected to be accessed by only one master and that the additional prefetching will present
data to the initiator in the same state as if the initial transaction were continued. This feature
should only be used in system designs that are able to ensure that the data provided to the master
has not been modified since the initial transaction.
A clear understanding of all the secondary side device’s device drivers and memory
architectures, and ensuring that the
PCI-to-PCI Bridge Architecture Specification
(Revision 2.0)
as stated in Chapter 5, sections 5.1
Prefetching Read Data
and 5.6.2
Stale Data
has been strongly adhered to, is required to prevent stale data from being
delivered to the master.
Summary of Contents for Tsi310TM
Page 8: ...Contents 8 Tsi310 User Manual 80B6020_MA001_05...
Page 10: ...List of Figures 10 Tsi310 User Manual 80B6020_MA001_05...
Page 12: ...List of Tables 12 Tsi310 User Manual 80B6020_MA001_05...
Page 18: ...18 Tsi310 User Manual 80B6020_MA001_05...
Page 44: ...2 Bus Operation 44 Tsi310 User Manual 80B6020_MA001_05...
Page 58: ...3 Clocking and Reset Options 58 Tsi310 User Manual 80B6020_MA001_05...
Page 62: ...4 Transaction Ordering 62 Tsi310 User Manual 80B6020_MA001_05...
Page 150: ...5 Configuration Registers 150 Tsi310 User Manual 80B6020_MA001_05...
Page 170: ...6 Signals and Pinout 170 Tsi310 User Manual 80B6020_MA001_05...
Page 190: ...7 JTAG Boundary Scan 190 Tsi310 User Manual 80B6020_MA001_05...
Page 196: ...8 Electrical Characteristics 196 Tsi310 User Manual 80B6020_MA001_05...
Page 200: ...9 Package Information 200 Tsi310 User Manual 80B6020_MA001_05...
Page 202: ...A Ordering Information 202 Tsi310 User Manual 80B6020_MA001_05...
Page 206: ...Index 206 Tsi310 User Manual 80B6020_MA001_05...