3. Clocking and Reset Options
55
Tsi310 User Manual
80B6020_MA001_05
3.9
Secondary Device Masking
The Tsi310 supports the masking of secondary devices through configuration/power strapping
of the secondary bus private device mask register. The process of converting Type 1
configuration transactions to Type 0 configuration transactions is modified by the contents of
the secondary bus private device mask register. A configuration transaction that targets a device
masked by this register is routed to device 15. Secondary bus architectures that are designed to
support masking of devices should not implement a device number 15 (that is, S_AD(31)).
The device mask bit options (device numbers 1, 4, 5, 6, 7, 9, and 13) defined by the bridge
allows architectures to support private device groupings that use a single or multiple interrupt
binding (for more information, see
PCI-to-PCI Bridge Architecture Specification
(Revision 2.0)
).
3.10
Handling of Address Phase Parity Errors
When an address parity error is detected by the Tsi310, the transaction will not be claimed (by
not asserting DEVSEL#) and is allowed to terminate with a master abort. The bridge will detect
address parity errors for all transactions on both the primary and secondary interfaces. The
result of an address parity error will be controlled by the parity error response bits in both the
command register and the bridge control register.
3.11
Optional Base Address Register
The 64-bit Base Address register located in the Tsi310 configuration space at offsets x'10' and
x'14' can optionally be used to acquire a 1 MB memory region at system initialization. The
PCI
2.2 specification
calls for the region that is defined by this register to be used by the bridge
itself. The Tsi310 uses this register to claim an additional prefetchable memory region for the
secondary bus. When used in conjunction with the secondary device masking, this allows for the
acquisition of memory space for private devices that are not otherwise viewable by the system
software.
The Optional Base Address Register can be used by primary bus masters to access locations on
the secondary side of the bridge only. Accesses from the secondary interface are ignored by this
BAR whether they fall within or outside the 1 MB memory region.
Summary of Contents for Tsi310TM
Page 8: ...Contents 8 Tsi310 User Manual 80B6020_MA001_05...
Page 10: ...List of Figures 10 Tsi310 User Manual 80B6020_MA001_05...
Page 12: ...List of Tables 12 Tsi310 User Manual 80B6020_MA001_05...
Page 18: ...18 Tsi310 User Manual 80B6020_MA001_05...
Page 44: ...2 Bus Operation 44 Tsi310 User Manual 80B6020_MA001_05...
Page 58: ...3 Clocking and Reset Options 58 Tsi310 User Manual 80B6020_MA001_05...
Page 62: ...4 Transaction Ordering 62 Tsi310 User Manual 80B6020_MA001_05...
Page 150: ...5 Configuration Registers 150 Tsi310 User Manual 80B6020_MA001_05...
Page 170: ...6 Signals and Pinout 170 Tsi310 User Manual 80B6020_MA001_05...
Page 190: ...7 JTAG Boundary Scan 190 Tsi310 User Manual 80B6020_MA001_05...
Page 196: ...8 Electrical Characteristics 196 Tsi310 User Manual 80B6020_MA001_05...
Page 200: ...9 Package Information 200 Tsi310 User Manual 80B6020_MA001_05...
Page 202: ...A Ordering Information 202 Tsi310 User Manual 80B6020_MA001_05...
Page 206: ...Index 206 Tsi310 User Manual 80B6020_MA001_05...