3. Clocking and Reset Options
53
Tsi310 User Manual
80B6020_MA001_05
, the terms “P_cycles” and “S_cycles” refer to clock cycles whose period is
determined by the P_CLK and S_CLK input frequencies, respectively. Since the time periods
listed in the table are based on counters, different clock rates will result in different effective
delays, as shown. The counter values have been selected to meet the various minimum delay
requirements, but will result in longer times when the clock period lengthens.
3.7
Bus Parking and Bus Width Determination
On the secondary interface, as required by the
PCI-to-PCI Bridge Architecture Specification
(Revision 2.0)
, the S_AD(31:0), S_C/BE(3:0), and PAR signals will be driven to zeros
whenever S_RST# is asserted. This is known as bus parking. The signals are driven low within
a few cycles of the falling edge of S_RST#; they are released (placed in the high-Z state) in the
cycle following the rising edge of S_RST#.
The Tsi310 is also required to drive S_REQ64# low for at least ten cycles prior to the
de-assertion of S_RST#, to allow devices to determine whether they are connected on a 64-bit
data path or a 32-bit data path. For convenience, this is done coincident with the broadcasting of
the initialization pattern, as shown in
.
Table 7: Delay Times for De-assertion of S_RST#
PCI
PCI-X (66 MHz)
PCI-X (100 MHz)
PCI-X (133 MHz)
T
pirstdly
7 P_cycles
6678 P_cycles
100
s - 133
s
13350 P_cycles
133
s - 200
s
13350 P_cycles
100
s - 133
s
T
xcap
6675 P_cycles
6675 P_cycles
100
s - 133
s
13347 P_cycles
133
s - 200
s
13347 P_cycles
100
s - 133
s
T
srstdly
11 S + 7 P_cycles
11 S + 7 P_cycles
11 S + 7 P_cycles
11 S + 7 P_cycles
T
sirstdly
16 S_cycles
6687 S_cycles
100
s - 133
s
13359 S_cycles
133
s - 200
s
13359 S_cycles
100
s - 133
s
Summary of Contents for Tsi310TM
Page 8: ...Contents 8 Tsi310 User Manual 80B6020_MA001_05...
Page 10: ...List of Figures 10 Tsi310 User Manual 80B6020_MA001_05...
Page 12: ...List of Tables 12 Tsi310 User Manual 80B6020_MA001_05...
Page 18: ...18 Tsi310 User Manual 80B6020_MA001_05...
Page 44: ...2 Bus Operation 44 Tsi310 User Manual 80B6020_MA001_05...
Page 58: ...3 Clocking and Reset Options 58 Tsi310 User Manual 80B6020_MA001_05...
Page 62: ...4 Transaction Ordering 62 Tsi310 User Manual 80B6020_MA001_05...
Page 150: ...5 Configuration Registers 150 Tsi310 User Manual 80B6020_MA001_05...
Page 170: ...6 Signals and Pinout 170 Tsi310 User Manual 80B6020_MA001_05...
Page 190: ...7 JTAG Boundary Scan 190 Tsi310 User Manual 80B6020_MA001_05...
Page 196: ...8 Electrical Characteristics 196 Tsi310 User Manual 80B6020_MA001_05...
Page 200: ...9 Package Information 200 Tsi310 User Manual 80B6020_MA001_05...
Page 202: ...A Ordering Information 202 Tsi310 User Manual 80B6020_MA001_05...
Page 206: ...Index 206 Tsi310 User Manual 80B6020_MA001_05...