IDT Tsi310TM, User Manual

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5. Configuration Registers 65
Tsi310 User Manual
80B6020_MA001_05
5.2 Register Map
The following table contains a map of Tsi310’s registers in the PCI Configuration Space. The
reserved registers and bits return zeros when read.
Table 11: Register Map
Bits/Register Names
Starting
Address Region Subregion 31:24 23:16 15:08 07:00
Device ID Vendor ID x‘00’ PCI
Configuration
Space Header
Region
(64 bytes)
PCI Device
Independent
Region
(16 bytes)
Status Command x‘04’
Class Code Revision ID x‘08’
BIST Header Type Latency Timer Cache Line
Size
x‘0C’
Base Address Register 0 x‘10’ PCI Device
Header Type
Region
(48 bytes)
Base Address Register 1 x‘14’
Secondary
Latency Timer
Subordinate
Bus Number
Secondary
Bus Number
Primary Bus
Number
x‘18’
Secondary Status I/O Limit I/O Base x‘1C’
Memory Limit Memory Base x‘20’
Prefetchable Memory Limit Prefetchable Memory Base x‘24’
Prefetchable Base Upper 32 Bits x‘28’
Prefetchable Limit Upper 32 Bits x‘2C’
I/O Limit Upper 16 Bits I/O Base Upper 16 Bits x‘30’
Reserved Capabilities
Pointer
x‘34’
Expansion ROM Base Addresses x‘38’
Bridge Control Interrupt Pin Interrupt Line x‘3C’