IDT Tsi310TM, User Manual

Page: 161 / 207

6. Signals and Pinout 161
Tsi310 User Manual
80B6020_MA001_05
6.6 Power and Ground Connections
6.6.1 Filter Requirements for P_VDDA and S_VDDA
For each Tsi310 VDDA pin, IDT recommends the use of a series ferrite bead and a 0.1µf
capacitor to ground (see
Figure 5 ). The Tsi310 has two PLLs, so there should be two separate
filter circuits: one for P_VDDA and the other for S_VDDA. Since there are no separate analog
ground pins, voltage islands and/or cutouts are not needed. Filter components should be placed
as close as possible to their respective VDDA pins, and then connected with wide tracks that are
as short as possible. The necessary characteristics for inductor L1 can be found in
Table 18 and
Figure 6 .
Figure 5: Filter Requirements for P_VDDA and S_VDDA
Table 17: Power and Ground Connections
Input Name
Number
of Pins Description
P_VDDA
a
a. A filtering circuit may be required to ensure a quiet supply at this pin (for more information, see the following section).
1 Quiet 2.5 V power supply connection to the PLL for the primary clock domain.
S_VDDA
a
1 Quiet 2.5 V power supply connection to the PLL for the secondary clock domain.
VDD 16 2.5 V power supply connections for the internal logic.
VDD2 26 3.3 V power supply connections for the I/O circuits.
GND 48 Ground connections.
Total 92
2.5V
Inductor L1
Capacitor
C1
0.1 µF
X7R
n_VDDA
GND
70 ohms @ 100 MHz