5. Configuration Registers
141
Tsi310 User Manual
80B6020_MA001_05
5.5.22
Primary Bus Downstream Split Transaction Register
This register controls the behavior of the bridge buffers when forwarding split transactions from
a primary bus requester to a secondary bus completer. When the completer bus is in PCI-X
mode, the split transaction commitment limit field only affects the byte count used when issuing
read requests.
Address Offset
x‘8C’
Access
See bit descriptions
Reset Value
x‘0020 0020’
Split Transaction Commitment Limit
Split Transaction Capacity
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Bit(s)
Access
Field Name and Description
31:16
RW
Split Transaction Commitment Limit
This field indicates the cumulative sequence size for all memory read transactions forwarded
by the bridge from requesters on the primary bus addressing completers on the secondary bus.
This field indicates the size of the commitment limit in units of ADQs.
Software is permitted to program this field to any value greater than or equal to the contents of
the Split transaction capacity field described below. A value less than the contents of the split
transaction capacity field causes unspecified results. The Tsi310 will forward split requests as
shown below according to the value programmed in the Split transaction Commitment Limit
field:
x`0020’
Split Transaction Commitment Limit Value < x‘0100’ the maximum request amount is
512 bytes. Larger transfers will be decomposed into a series of smaller transfers, until the
original byte count has been satisfied.
Any value
x‘0100’programmed in the Split Transaction Commitment Limit field causes the
Tsi310 to forward all split requests of any size regardless of the amount of buffer space
available. When the Tsi310 is programmed with a value greater than or equal to x‘0100’ large
bursts are not decomposed; the entire byte-count received will be requested.
Software is permitted to change this field at any time. The most recent value of the field is used
each time the bridge forwards a split transaction.
The state of this field after a RST# is the same as the split transaction capacity field.
15:0
RO
Split Transaction Capacity
This read-only field indicates the size of the buffer (in number of ADQs) for storing split
completions for memory reads for requesters on the primary bus addressing completers on the
secondary bus.
The bridge returns x‘0020’ to indicate that there are 32 ADQs (4K bytes) available buffer space.
Summary of Contents for Tsi310TM
Page 8: ...Contents 8 Tsi310 User Manual 80B6020_MA001_05...
Page 10: ...List of Figures 10 Tsi310 User Manual 80B6020_MA001_05...
Page 12: ...List of Tables 12 Tsi310 User Manual 80B6020_MA001_05...
Page 18: ...18 Tsi310 User Manual 80B6020_MA001_05...
Page 44: ...2 Bus Operation 44 Tsi310 User Manual 80B6020_MA001_05...
Page 58: ...3 Clocking and Reset Options 58 Tsi310 User Manual 80B6020_MA001_05...
Page 62: ...4 Transaction Ordering 62 Tsi310 User Manual 80B6020_MA001_05...
Page 150: ...5 Configuration Registers 150 Tsi310 User Manual 80B6020_MA001_05...
Page 170: ...6 Signals and Pinout 170 Tsi310 User Manual 80B6020_MA001_05...
Page 190: ...7 JTAG Boundary Scan 190 Tsi310 User Manual 80B6020_MA001_05...
Page 196: ...8 Electrical Characteristics 196 Tsi310 User Manual 80B6020_MA001_05...
Page 200: ...9 Package Information 200 Tsi310 User Manual 80B6020_MA001_05...
Page 202: ...A Ordering Information 202 Tsi310 User Manual 80B6020_MA001_05...
Page 206: ...Index 206 Tsi310 User Manual 80B6020_MA001_05...