IDT Tsi310TM, User Manual

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5. Configuration Registers 130
Tsi310 User Manual
80B6020_MA001_05
5.5.14 Opaque Memory Limit Register
This register specifies upper address bits 31:20 of the opaque memory address range. It is used
in conjunction with the opaque memory base register, the opaque memory base upper 32 bits
register, and the opaque memory limit upper 32 bits register to specify a range of 64-bit
addresses that are used exclusively on the secondary bus. These memory addresses will not be
accepted by the bridge on the primary or the secondary buses. This address range is enabled by
bit 0 of the opaque memory enable register. Bits 19:0 of the limit address are assumed to be
x‘F FFFF’. This register also specifies that the bridge supports 64-bit opaque memory
addressing.
Address Offset x‘76’
Access See individual fields
Reset Value x‘FFF1’
Opaque Memory Limit Address 64-bit
addressing
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit(s) Access Field Name and Description
15:4 RW Opaque Memory Limit Address
Address bits 31:20 of the limit address for the opaque memory address range. Memory
operations in this range are not accepted by the bridge on either the primary or secondary
interfaces.
3:0 RO Set to b‘0001’ to indicate support of 64-bit addressing.