IDT Tsi310TM, User Manual

Page: 158 / 207

6. Signals and Pinout 158
Tsi310 User Manual
80B6020_MA001_05
P_CFG_BUSY I 1 Primary Configuration Busy: Controls the reset and power up value of
bit 2 of the miscellaneous control register. Used to sequence
initialization with regard to the primary and secondary buses for
applications that require access to the bridge configuration registers
from the secondary bus. When pulled high, the configuration
commands received on the primary bus are retried until such time as
bit 2 of the miscellaneous control register is set to b‘0’ by a
configuration write initiated from the secondary bus. Applications that
do not require access to the bridge configuration registers from the
secondary bus should pull this signal to ground.
0 = Reset value of bit 2 of the miscellaneous control register is b‘0’.
1 = Reset value of bit 2 of the miscellaneous control register is b‘1’.
Note: When designing a Tsi310-based system, see the Tsi310 Device
Errata document for more information about the P_CFG_BUSY
signal.
P_DRVR_MODE I 1 Primary Driver Mode Control: Used to alter the output impedance of
the primary bus PCI/PCI-X drivers, to account for how many drops are
on the bus. This line should be pulled through a resistor to a high or a
low as needed. Internal pull down.
0 = Use the default impedance value.
1 = Select the alternate impedance value.
RESERVED2 1 Reserved pin: This signal should be pulled to ground.
S_DRVR_MODE I 1 Secondary Driver Mode Control: Used to alter the output impedance
of the secondary bus PCI/PCI-X drivers, to account for how many
drops are on the bus. This line should be pulled through a resistor to a
high or a low as needed. Internal pull down.
0 = Use default impedance value.
1 = Select alternate impedance value.
S_CLK_STABLE I 1 S_CLK Input Stable: Indicates when the S_CLK input to the bridge is
stable. It determines when the S_RST# signal may be de-asserted.
0 = S_CLK input is not yet stable
1 = S_CLK input is stable
S_IDSEL I 1 Initialization Device Select: Used as a chip select during configuration
read and write transactions on the secondary bus. Applications that
do not require access to the bridge configuration registers from the
secondary bus should pull this pin low.
Table 15: Strapping Pins and Other Signals (Continued)
Signal Name
a
I/O Width Description