IDT Tsi310TM, User Manual

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2. Bus Operation 36
Tsi310 User Manual
80B6020_MA001_05
2.3.5 Prefetchable Reads
A prefetchable read transaction is a read transaction where the Tsi310 performs speculative
reads, transferring data from the target before it is requested from the initiator. This behavior
allows a prefetchable read transaction to consist of multiple data transfers. For prefetchable read
transactions, all byte enables are asserted for all data phases.
Prefetchable behavior is used for memory read line and memory read multiple transactions, as
well as for memory read transactions that fall into prefetchable memory space and are allowed
to fetch more than a DWord. The amount of data that is prefetched depends on the type of
transaction and the setting of bits in the primary and secondary data buffering control registers
in configuration space. The amount of prefetching may also be affected by the amount of free
buffer space available in the Tsi310, and by any read address boundaries encountered. Examples
of these boundaries are cache line for cache line reads and 1M address boundary to ensure that a
read does not cross into another devices’ space.
2.3.5.1 Algorithm for PCI-to-PCI Mode
The algorithm used for transfers in PCI-to-PCI mode is user defined in the primary and
secondary data buffering control registers. These registers have bits for memory read to
prefetchable space, memory read line, and memory read multiple transactions. For memory
read, the bits select whether to read a DWord, read to a cache line boundary, or to fill the
prefetch buffer. For memory read line and memory read multiple transactions, the bits select
whether to read to a cache line boundary or to fill the prefetch buffer. In all cases, if the bits are
selected to fill the prefetch buffer, the maximum amount of data that is requested on the target
interface is controllable by the setting of the maximum memory read byte count bits of the
Primary and Secondary Data Buffering Control registers. When more than 512 bytes are
requested, the Tsi310 fetches data to fill the buffer and then fetches more data to keep the buffer
filled as sectors (128 bytes) are emptied and become free to use again.
2.3.5.2 Algorithm for PCI-to-PCI-X Mode
The algorithm for transfers in this mode is much the same as for transfers in PCI-to-PCI mode,
except that the maximum request amount may be additionally constrained by the setting of the
split transaction commitment limit value in the upstream or downstream split transaction
register. The only other difference is that prefetching will not cease when the originating master
disconnects. Prefetching will only cease when all of the requested data is received, as required
by the PCI-X architecture.