IDT Tsi310TM, User Manual

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5. Configuration Registers 81
Tsi310 User Manual
80B6020_MA001_05
5.4.11 Lower Memory Base Address Register
This register and the memory space defined by it are enabled by the strapping pin, BAR_EN.
When the BAR_EN pin is pulled low, this register location returns zeros for reads and cannot be
written. When the BAR_EN pin is pulled high, the lower memory base address register specifies
address bits 31:20 of the 64-bit memory base address register. Bits 3:0 are encoded to indicate
that this is part of a 64-bit register, and that it defines a prefetchable memory space.
Memory accesses on the primary bus are compared against this register, if address bits 63:20 are
equal to bits 63:20 of the address defined by the combination of the lower memory base address
register and the upper memory base address register, the access is claimed by the bridge and
passed through to the secondary bus.
Memory accesses on the secondary bus are also compared against this register, if address bits
63:20 are equal to bits 63:20 of the address defined by the combination of the lower memory
base address register and the upper memory base address register, the access is ignored by the
bridge.
The Optional Base Address Register can be used by primary bus masters to access locations on
the secondary side of the bridge only. Accesses from the secondary interface are ignored by this
BAR whether they fall within or outside the 1 MB memory region.
Address Offset x‘10’
Access See individual fields
Reset Value x‘0000 000C’ When BAR_EN (pin G2) is tied high. For more
information on strapping considerations, see
Section 6.4 on
page 157 .
x‘0000 0000’ When BAR_EN (pin G2) is tied low. For more
information on strapping considerations, see
Section 6.4 on
page 157 .
Lower Memory Base Address Reserved
Pr
efetc
h
able indicator
Deco
der W
idth
De
coder
T
y
pe
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0