IDT Tsi310TM, User Manual

Page: 137 / 207

5. Configuration Registers 137
Tsi310 User Manual
80B6020_MA001_05
5.5.20 PCI-X Bridge Status Register
This register identifies the capabilities and current operating mode of the bridge on its primary
bus.
Address Offset x‘84’
Access See individual bit descriptions. Reads to this register behave
normally. Writes are slightly different in that bits can be reset,
but not set. A bit is reset whenever the register is written, and
the data in the corresponding bit location is a ‘1’.
Reset Value x‘0003 00F8’
Reserved S
p
lit Requ
est Del
a
yed
S
p
lit Comple
tio
n
Overrun
Unexp
e
cte
d
S
p
lit
C
o
mple
tio
n
S
p
lit Comple
tio
n
Discarde
d
133
MHz
Cap
a
ble
64-bi
t Devi
ce
Bus N
u
mber
Device Num
b
er
Fu
ncti
on Numbe
r
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit(s) Access Field Name and Description
31:22 RO Reserved
21 RW Split Request Delayed
This bit is set any time the bridge has a request to forward a transaction to the primary bus, but
cannot because there is not enough room within the limit specified in the split transaction
commitment limit field in the upstream split transaction control register. It is used by algorithms
that optimize the setting of the upstream split transaction commitment limit register.
0 = The bridge has not delayed a split request.
1 = The bridge has delayed a split request.
20 RW Split Completion Overrun
This bit is set if the bridge terminates a Split Completion on the primary bus with retry or
disconnect at next ADB because the bridge buffers are full. It is used by algorithms that
optimize the setting of the upstream split transaction commitment limit register.
0 = The bridge has accepted all split completions.
1 = The bridge has terminated a split completion with retry or disconnect at next ADB because
the bridge buffers were full.