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8. Maintenance, Checkout, and Calibration
8.10. FIM Self-Test Diagnostic Codes
354
Experion PKS Series A Fieldbus Interface Module User's Guide
R400
Honeywell
July
2010
Test Code
Target Device(s)
Failure Modes
Function
Interrupt Test
daughterboard is not asserted.
ICP ASIC and Shared RAM Diagnostics
T100
ICP ASIC
Initialization Test
ICP ASIC, ICP,
Oscillator, PLD,
CPU
Insures that ICP_Fault signal is
asserted as IRQ1, releases ICP
ASIC from RESET, insures that
ICP_FAULT clears within a
appropriate amount of time, writes
hardware initialization parameters
to ASIC, insures that ICP_FAULT
is not asserted.
T101
ICP RAM Byte
Access Test
RAM, PLD, CPU,
buffers
Verifies that writing a string of 8
bytes can be read back bytes and
as 2 correct words.
T102
ICP RAM Parity
Interrupt Test
RAM, PLD, CPU,
buffers
Prove that a shared RAM parity
error can be genereated and
recognized by the CPU for
odd/even parity bit on each byte
lane. Shared RAM parity is
enabled from this test on.
T103
ICP RAM Word
Read Test
RAM, PLD, CPU,
buffers
Verifies that word patterns can be
written and read back as words.
T104
ICP RAM Byte
Read Test
RAM, PLD, CPU,
buffers
Verifies that word patterns can be
written and read backs a bytes.
T105
ICP RAM Byte
Read Test
RAM, PLD, CPU,
buffers
Verifies that word patterns can be
written and read back as
halfwords.
T106
ICP RAM Half Write
Test
RAM, PLD, CPU,
buffers
Verifies that halfwords can be
written.
T107
ICP RAM Half Align
Test
RAM, PLD, CPU,
buffers
Verifies that halfwords can be
written, misaligned, and read back
as halfwords and words.
T108
ICP RAM Word
Align Test
RAM, PLD, CPU,
buffers
Verifies that words can be written
and read when misaligned.
T109
ICP RAM Unique
Address Test
RAM, PLD, CPU,
buffers
Verifies that each address can be
accessed uniquely. Runs with data
parity enabled and fatal.
Summary of Contents for Experion PKS Series A
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