Detailed Description
8500C/8500C+ System Maintenance Manual
4-3
Both of the initial sections are implemented with precision resistors, capacitors, and a
high-quality operational amplifier. This stage provides two functions. Its Q and corner
frequency are set so that it contributes to the overall ten-pole low-pass response. Its corner
frequency is low enough such that it also functions as an anti-alias filter for the following
sampled data filter section.
The middle three sections are implemented with general purpose switched capacitor
filters. The filter characteristics of these three sections are set by precision resistors and a
crystal-controlled realtime clock on the digital board. The corner frequency of these
sections is changed under program control, allowing them to be used during both low- and
high-range frequency analysis.
The final second-order filter section is similar to the first: it is actually side-by-side low-
and high-frequency sections. The same control line that selects the low- or high-frequency
filter output format on the first sections also selects the related filter output from the final
filter section.
e.
Programmable Gain Amplifier. The programmable gain amplifier is a high resolution
amplifier which follows the first second-order analog anti-alias filter section.
The gain programming is managed by the system firmware. The firmware continually
monitors the incoming signal level, and adjusts the gain for optimum digitization
resolution and maximum signal-to-noise ratio. The position of the gain stage following the
first stage low-pass filter ensures that only in-band signals are amplified, further
enhancing the signal-to-noise characteristics. Up to 4080 different gain settings can be
selected from a gain of one to 512.
f.
Track and Hold. The track and hold circuit tracks the filtered input signal and holds it until
ready for conversion by the analog-to-digital converter.
g.
Analog-to-Digital Converter. The analog-to-digital converter (ADC) is a monolithic, 10-
bit ADC that digitizes the filtered and amplified input signal. The ADC performs
conversions at rates as high as 40,000 conversions per second under the command of the
digital board timing controller. The conversion resolution of the 10-bit ADC allows
simultaneous measurement of signal components differing in amplitude by as much 60
dB. The digitized data signal is applied to the digital board memory via the 10-bit system
bus.
h.
Overload Detectors. The analog board contains two overload detectors, an input signal
level detector, and a gain amplifier signal level detector. The input overload detector
allows the system firmware to detect and report to the user any occurrences of signal
corruption caused by input signal overload.
The gain overload detector allows the system firmware to detect occurrences of
overdriving by the programmable gain amplifier. The firmware then lowers the gain of the
programmable gain amplifier to prevent signal distortion.
