Rev. 1.10
56
October 23, 2020
Rev. 1.10
57
October 23, 2020
BC66F5652
2.4GHz RF Transceiver A/D Flash MCU
BC66F5652
2.4GHz RF Transceiver A/D Flash MCU
The internal page buffer will be cleared by hardware after power on reset. When the EEPROM
write enable control bit, namely WREN, is changed from “1” to “0”, the internal page buffer will
also be cleared. Note that when the WREN bit is changed from “0” to “1”, the internal page buffer
will not be cleared. A page write is initiated in the same way as a byte write initiation except that
the EEPROM data can be written up to 16 bytes. The EEPROM address lower 4 bits are internally
incremented by one following the reception of each data byte in the page write mode. The EEPROM
address higher 3 bits used to specify the desired page location will not be incremented. When the
word address, internally generated, reaches the page boundary, namely 0FH, the EEPROM address
will stop at 0FH. The EEPROM address will not
“
roll over”. At this point any data write operations
to the EED register will be invalid.
For page-write operations the the start address of the desired EEPROM page m
ust first be placed
in the EEA register and the data placed in the EED register. The maximum data length for a page
is 16 bytes. Note that when a data byte is written into the EED register, then the data in the EED
register will be loaded into the internal page buffer and the current address value will automatically
be incremented by one. When the page data is completely written into the page buffer,
then the write
enable bit, WREN, in the EEC register must first be set high to enable the write function. After this,
the WR bit in the EEC register must be immediately set high to initiate a write cycle. These two
instructions must be executed in two consecutive instruction cycles. The global interrupt bit EMI
should also first be cleared before implementing any write operations, and then set again after a
valid write activation procedure has completed. Note that setting the WR bit high will not initiate a
write cycle if the WREN bit has not been set.
As the EEPROM write cycle is controlled using an internal timer whose operation is asynchronous
to microcontroller system clock, a certain time will elapse before the data will have been written into
the EEPROM. Detecting when the write cycle has finished can be implemented either by polling the
WR bit in the EEC register or by using the EEPROM interrupt. When the write cycle terminates,
the WR bit will be automatically cleared to zero by the microcontroller, informing the user that the
data has been written to the EEPROM. The application program can therefore poll the WR bit to
determine when the write cycle has ended. After the write operation is finished, the WREN bit will
be set low by hardware.
Write Protection
Protection against inadvertent write operation is provided in several ways. After the device is
powered-on the Write Enable bit in the control register will be cleared preventing any write
operations. Also at power-on the Memory Pointer high byte register, MP1H or MP2H, will be reset
to zero, which means that Data Memory Sector 0 will be selected. As the EEPROM control register
is located in Sector 1, this adds a further measure of protection against spurious write operations.
During normal program operation, ensuring that the Write Enable bit in the control register is
cleared will safeguard against incorrect write operations.
EEPROM Interrupt
The EEPROM write interrupt is generated when an EEPROM erase or write cycle has ended. The
EEPROM interrupt must first be enabled by setting the DEE bit in the relevant interrupt register.
However, as the EEPROM interrupt is contained within a Multi-function Interrupt, the associated
multi-function interrupt enable bit must also be set. When an EEPROM erase or write cycle ends,
the DEF request flag and its associated multi-function interrupt request flag will both be set high. If
the global, EEPROM and multi-function interrupts are enabled and the stack is not full, a jump to
the associated Multi-function Interrupt vector will take place. When the interrupt is serviced only
the Multi-function interrupt flag will be automatically reset, the EEPROM interrupt flag must be
manually reset by the application program. The EMI bit will also be automatically cleared to disable
other interrupts. More details can be obtained in the Interrupts section.
