Rev. 1.10
98
October 23, 2020
Rev. 1.10
99
October 23, 2020
BC66F5652
2.4GHz RF Transceiver A/D Flash MCU
BC66F5652
2.4GHz RF Transceiver A/D Flash MCU
• CTMAH Register
Bit
7
6
5
4
3
2
1
0
Name
D15
D14
D13
D12
D11
D10
D9
D8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
D15~D8
: CTM CCRA High Byte Register bit 7 ~ bit 0
CTM 16-bit CCRA bit 15 ~ bit 8
• CTMRP Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
D7~D0
: CTM CCRP 8-bit register, compared with the CTM Counter bit 15 ~ bit 8
Comparator P Match Period =
0: 65536 CTM clocks
1~255: 256×(1~255) CTM clocks
These eight bits are used to setup the value on the internal CCRP 8-bit register, which
are then compared with the internal counter
’
s highest eight bits. The result of this
comparison can be selected to clear the internal counter if the CTCCLR bit is set to
zero. Setting the CTCCLR bit to zero ensures that a compare match with the CCRP
values will reset the internal counter. As the CCRP bits are only compared with the
highest eight counter bits, the compare values exist in 256 clock cycle multiples.
Clearing all eight bits to zero is in effect allowing the counter to overflow at its
maximum value.
Compact Type TM Operating Modes
The Compact Type TM can operate in one of three operating modes, Compare Match Output Mode,
PWM Output Mode or Timer/Counter Mode. The operating mode is selected using the CTM1 and
CTM0 bits in the CTMC1 register.
Compare Match Output Mode
To select this mode, bits CTM1 and CTM0 in the CTMC1 register, should be set to “00”
respectively. In this mode once the counter is enabled and running it can be cleared by three
methods. These are a counter overflow, a compare match from Comparator A and a compare match
from Comparator P. When the CTCCLR bit is low, there are two ways in which the counter can be
cleared. One is when a compare match occurs from Comparator P, the other is when the CCRP bits
are all zero which allows the counter to overflow. Here both CTMAF and CTMPF interrupt request
flags for the Comparator A and Comparator P respectively, will both be generated.
If the CTCCLR bit in the CTMC1 register is high then the counter will be cleared when a compare
match occurs from Comparator A. However, here only the CTMAF interrupt request flag will be
generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when
CTCCLR is high no CTMPF interrupt request flag will be generated. If the CCRA bits are all zero,
the counter will overflow when it reaches its maximum 16-bit, FFFF Hex, value, however here the
CTMAF interrupt request flag will not be generated.
As the name of the mode suggests, after a comparison is made, the CTM output pin will change
state. The CTM output pin condition however only changes state when a CTMAF interrupt request
flag is generated after a compare match occurs from Comparator A. The CTMPF interrupt request
flag, generated from a compare match occurs from Comparator P, will have no effect on the CTM
