Rev. 1.10
206
October 23, 2020
Rev. 1.10
207
October 23, 2020
BC66F5652
2.4GHz RF Transceiver A/D Flash MCU
BC66F5652
2.4GHz RF Transceiver A/D Flash MCU
Functional Description
2.4GHz RF Transceiver
The RF Transceiver adopts a fully-integrated, low-IF receiver architecture. The received RF signal
is first amplified by a low noise amplifier (LNA), after which the frequency is down-converted to an
intermediate frequency (IF) by a quadrature mixer. The mixer output is filtered by a channel-selected
filter which rejects the unwanted out-of-band (OOB) interference and image signals. After filtering,
the IF signal is amplified by an analog programmable gain amplifier (PGA). Then the IF signal is
digitized by a 9-bit Σ∆ ADC.
The RF Transceiver features an Automatic Gain Control (AGC) unit to adjust the receiver gain
according to the RSSI, generated at the digital modem. The AGC enables the RF Transceiver to
operate from sensitivity level to +10dBm input power.
The RF Transceiver adopts a fully integrated fractional-N synthesizer which includes RF VCO, loop
filter and a digital controlled XO (DCXO). The fractional-N synthesizer architecture allows the users
to extend their potential usage to a wider frequency range.
The transmit session is a VCO direct modulation architecture. Different from the conventional
direct up-conversion transmitters, the GFSK modulation signal is fed into the VCO directly to take
advantage of fractional-N synthesizer. As a result, both layout area and current consumption are
much smaller compared with direct up-conversion transmitters. The fine resolution can generate
a low FSK error GFSK signal. The modulated signal is fed into a Power Amplifier (PA) and the
maximum output power can be up to +6dBm.
Data Control Interface – Serial Interface (SPI)
The RF Transceiver communicates with the device via a 3-wire SPI interface (CSN, SCK, SDIO)
or a 4-wire SPI interface (SDO on GIO2 line or GIO3~GIO4) with a data rate up to 8Mbps. An
SPI transmission is an (8+8×n) bits sequence which consists of an 8-bit command and n×8 bits of
data, where n can be 0 or any natural number. If the number n is greater than the address boundary,
the address will return to zero. The device should pull the CSN (SPI chip select) pin low state in
order to access the RF Transceiver. Using the SPI interface, user can access the control registers and
issue Strobe commands. When writing data to the RF module, the SPI data will be latched into the
registers at the rising edge of the SCK signal. When reading data from the RF registers, the bit data
will be transferred at the falling edge of the SCK signal after the target register address has been
input.
Command (8 Bits)
Data (8 Bits)
C7
C6
C5
C4
C3
C2
C1
C0
D7
D6
D5
D4
D3
D2
D1
D0
SPI Command Format
Two kinds of command are defined. One is 1-byte command only, named CmdO, and the other is
1-byte command followed by n-byte data, named CmdD.
C7 C6 C5 C4 C3 C2 C1 C0
Description
CmdO CmdD Data Bytes
0
1
A5 A4 A3 A2 A1 A0 Write Control Register
√
1
1
1
A5 A4 A3 A2 A1 A0 Read Control Register
√
1
0
0
1
0
0
0
B1 B0 Set Register Bank
√
0
0
0
0
1
0
0
0
0 Write PRX Pipe 0 Address
Write PTX Address
√
3~5
1
0
0
1
0
0
0
0 Read PRX Pipe 0 Address
Read PTX Address
√
3~5
0
0
0
1
0
0
0
1 Write TX FIFO with Auto-ACK Mode
Command
√
1~32
