Rev. 1.10
214
October 23, 2020
Rev. 1.10
215
October 23, 2020
BC66F5652
2.4GHz RF Transceiver A/D Flash MCU
BC66F5652
2.4GHz RF Transceiver A/D Flash MCU
out” mode. The TX FIFO in a PRX device will be used to acknowledge the corresponding pipe.
The RX FIFO in a PRX device can contain the received payloads from up to three different PTX
devices. If RX FIFOs are full, the new receiving data on-air will be lost. Users can use “Read RX
FIFO Command” to read RX payloads in both PTX and PRX devices. The STATUS register shows
the FIFO’s status.
FIFO Flush
If link layer failed or other reasons cause FIFO data useless, users can use “TX FIFO Flush
Command” to reset the TX FIFO, or use the “RX FIFO Flush Command” to reset the RX FIFO.
After using the flush command, the FIFO’s status will be empty.
Interrupt
The RF Transceiver has an Interrupt Request (IRQ) pin which is low active and is activated when
TX_DS IRQ, RX_DR IRQ or MAX_RT IRQ in the IRQ1 register is set high by the state machine.
The IRQ pin is reset when the MCU writes ‘1’ to the IRQ source bit in the IRQ1 register. The IRQ
mask in the MASK register is used to select the IRQ sources that are allowed to assert the IRQ pin.
By setting one of the mask bits high, the corresponding IRQ source is disabled. All IRQ sources are
enabled by default.
The 3-bit pipe information in the IRQ1 register is updated during the IRQ pin high to low transition. If
the IRQ1 register is read during an IRQ pin high to low transition, the pipe information is unreliable.
One-to-Six Star Network
The RF Transceiver can be configured as PRX that can receives data from up to 6 different
data pipes at one frequency. Each pipe has its own data pipe address. The address length can be
configured as 3~5 bytes long and all data pipes adopt the same address length configuration. Up to 6
PTX devices with different addresses can communicate with a PRX.
For the PRX side, the data pipes are enabled with the bits in the PEN register. Only data pipe 0 and
1 are enabled by default.
Pipe 0 address is written by the Write PRX Pipe 0 Address Command. Pipe 1 address is written by
the Write PRX Pipe1 Address Command. The data pipe 0 has a unique full address setting. The most
significant 16 bits of the address cannot be the same for pipe 0 and pipe 1. The LSByte of pipe 2~5
addresses are set by writing the PnB0 (n=2~5) control registers. The data pipes 1~5 share the same
most four significant address bytes and are distinguished by a different least significant address byte.
The following table lists a PRX pipe address setting example.
Byte4
Byte3
Byte2
Byte1
Byte0
Data pipe 0 (Strobe Command Pipe 0)
0xF1
0xD2
0xE6
0xA2
0x33
Data pipe 1 (Strobe Command Pipe 1)
0x7F
0xFE
0x8E
0x47
0xD3
Data pipe 2 (P2B0)
↑
↑
↑
↑
0xD4
Data pipe 3 (P3B0)
↑
↑
↑
↑
0xD5
Data pipe 4 (P4B0)
↑
↑
↑
↑
0xD6
Data pipe 5 (P5B0)
↑
↑
↑
↑
0xD7
The data pipes are enabled, data pipe 0 has a 5-byte address and pipes 1 to 5 share the four most
significant address bytes, i.e., the address byte 1 to 4 are the same but the byte 0 of all six pipes’
addresses must be different.
When PRX receives a valid payload, it will record the corresponding PTX’s address. Then PRX uses
the recorded address to acknowledge PTX if the auto-acknowledgement feature is enabled. When
PTX uses pipe 0 for receiving acknowledge packet, the PTX needs to use the same address for pipe
0 and TX packet. The following diagram shows a setting example for PTX and PRX.
