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GD32E23x User Manual
526
Figure 18-55. I2S initialization sequence
Is the
MSTMOD
bit is 1
Start
YES
Configure the DIV [7:0] bits, the OF
bit, and the MCKOEN bit to define
the I2S bitrate and master clock
Finish
Configure the CKPL bit to define the clock polarity
of idle state
Configure the I2SSEL bit to select I2S mode
Configure the I2SSTD [1:0] bits and the PCMSMOD
bit to select I2S standard
Configure the I2SOPMOD [1:0] bits to select I2S
operation mode
Configure the DTLEN [1:0] bits and the CHLEN bit
to select I2S data format
Configure the TBEIE bit, the RBNEIE bit, the
ERRIE bit to enable I2S interrupt (optional)
Configure the DMATEN bit, and the DMAREN bit to
enable I2S DMA function (optional)
Configure the I2SEN bit to enable I2S
No