GigaDevice Semiconductor GD32E23 Series User Manual Download Page 147

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GD32E23x User Manual

147

8.5.

Register definition

DMA base address: 0x4002 0000

8.5.1.

Interrupt flag register (DMA_INTF)

Address offset: 0x00

Reset value: 0x0000 0000

This register has to be accessed by word(32-bit)

Reserved

ERRIF4 HTFIF4 FTFIF4

GIF4

ERRIF3 HTFIF3

FTFIF3

GIF3

ERRIF2 HTFIF2 FTFIF2

GIF2

ERRIF1 HTFIF1 FTFIF1

GIF1

ERRIF0 HTFIF0 FTFIF0

GIF0

Bits

Fields

Descriptions

31:20

Reserved

Must be kept at reset value

19/15/11/7/3 ERRIFx

Error flag of channel x (x=0

…4)

Hardware set and software cleared by configuring DMA_INTC register.

0: Transfer error has not occurred on channel x

1: Transfer error has occurred on channel x

18/14/10/6/2 HTFIFx

Half transfer finish flag of channel x (x=0

…4)

Hardware set and software cleared by configuring DMA_INTC register.

0: Half number of transfer has not finished on channel x

1: Half number of transfer has finished on channel x

17/13/9/5/1

FTFIFx

Full Transfer finish flag of channel x (x=0

…4)

Hardware set and software cleared by configuring DMA_INTC register.

0: Transfer has not finished on channel x

1: Transfer has finished on channel x

16/12/8/4/0

GIFx

Glo

bal interrupt flag of channel x (x=0…4)

Hardware set and software cleared by configuring DMA_INTC register.

0: None of ERRIF, HTFIF or FTFIF occurs on channel x

1: At least one of ERRIF, HTFIF or FTFIF occurs on channel x

8.5.2.

Interrupt flag clear register (DMA_INTC)

Address offset: 0x04

Reset value: 0x0000 0000

Summary of Contents for GD32E23 Series

Page 1: ...GigaDevice Semiconductor Inc GD32E23x Arm Cortex M23 32 bit MCU User Manual Revision 1 5 Jul 2022 ...

Page 2: ...2 1 5 4 EXTI sources selection register 2 SYSCFG_EXTISS2 33 1 5 5 EXTI sources selection register 3 SYSCFG_EXTISS3 35 1 5 6 System configuration register 2 SYSCFG_CFG2 38 1 5 7 IRQ Latency register SYSCFG_CPU_IRQ_LAT 39 1 6 Device electronic signature 39 1 6 1 Memory density information 40 1 6 2 Unique device ID 96 bits 40 2 Flash memory controller FMC 42 2 1 Overview 42 2 2 Characteristics 42 2 3...

Page 3: ...w 60 3 3 1 Backup domain 61 3 3 2 VDD VDDA power domain 62 3 3 3 1 2V power domain 64 3 3 4 Power saving modes 64 3 4 PMU registers 67 3 4 1 Control register PMU_CTL 67 3 4 2 Control and status register PMU_CS 68 4 Reset and clock unit RCU 72 4 1 Reset control unit RCTL 72 4 1 1 Overview 72 4 1 2 Function overview 72 4 2 Clock control unit CCTL 73 4 2 1 Overview 73 4 2 2 Characteristics 75 4 2 3 F...

Page 4: ...ster EXTI_EVEN 109 5 6 3 Rising edge trigger enable register EXTI_RTEN 110 5 6 4 Falling edge trigger enable register EXTI_FTEN 110 5 6 5 Software interrupt event register EXTI_SWIEV 111 5 6 6 Pending register EXTI_PD 112 6 General purpose and alternate function I Os GPIO and AFIO 113 6 1 Overview 113 6 2 Characteristics 113 6 3 Function overview 113 6 3 1 GPIO pin configuration 114 6 3 2 Alternat...

Page 5: ... 2 Free data register CRC_FDATA 135 7 4 3 Control register CRC_CTL 136 7 4 4 Initialization data register CRC_IDATA 137 7 4 5 Polynomial register CRC_POLY 137 8 Direct memory access controller DMA 138 8 1 Overview 138 8 2 Characteristics 138 8 3 Block diagram 139 8 4 Function overview 139 8 4 1 DMA operation 139 8 4 2 Peripheral handshake 141 8 4 3 Arbitration 142 8 4 4 Address generation 142 8 4 ...

Page 6: ...62 10 4 4 Routine sequence 162 10 4 5 Operation mode 162 10 4 6 Conversion result threshold monitor function 165 10 4 7 Data storage mode 165 10 4 8 Sample time configuration 167 10 4 9 External trigger configuration 167 10 4 10 DMA request 167 10 4 11 ADC internal channels 167 10 4 12 Programmable resolution DRES fast conversion mode 168 10 4 13 On chip hardware oversampling 168 10 4 14 ADC inter...

Page 7: ...ristics 187 12 1 3 Function overview 187 12 1 4 Register definition 190 12 2 Window watchdog timer WWDGT 194 12 2 1 Overview 194 12 2 2 Characteristics 194 12 2 3 Function overview 194 12 2 4 Register definition 197 13 Real time clock RTC 199 13 1 Overview 199 13 2 Characteristics 199 13 3 Function overview 200 13 3 1 Block diagram 200 13 3 2 Clock source and prescalers 201 13 3 3 Shadow registers...

Page 8: ...3 4 11 Date of time stamp register RTC_DTS 224 13 4 12 Sub second of time stamp register RTC_SSTS 224 13 4 13 High resolution frequency compensation register RTC_HRFC 225 13 4 14 Tamper register RTC_TAMP 226 13 4 15 Alarm 0 sub second register RTC_ALRM0SS 230 13 4 16 Backup registers RTC_BKPx x 0 4 231 14 Timer TIMERx 232 14 1 Advanced timer TIMERx x 0 233 14 1 1 Overview 233 14 1 2 Characteristic...

Page 9: ...6 5 TIMERx registers x 5 422 15 Infrared ray port IFRP 427 15 1 Overview 427 15 2 Characteristics 427 15 3 Function overview 427 16 Universal synchronous asynchronous receiver transmitter USART 429 16 1 Overview 429 16 2 Characteristics 429 16 3 Function overview 431 16 3 1 USART frame format 431 16 3 2 Baud rate generation 432 16 3 3 USART transmitter 433 16 3 4 USART receiver 434 16 3 5 Use DMA ...

Page 10: ...s register USART_RFCS 465 17 Inter integrated circuit interface I2C 467 17 1 Overview 467 17 2 Characteristics 467 17 3 Function overview 467 17 3 1 SDA and SCL lines 468 17 3 2 Data validation 469 17 3 3 START and STOP signal 469 17 3 4 Clock synchronization 469 17 3 5 Arbitration 470 17 3 6 I2C communication flow 470 17 3 7 Programming model 471 17 3 8 SCL line stretching 479 17 3 9 Use DMA for ...

Page 11: ...n 512 18 3 8 CRC function 512 18 3 9 SPI interrupts 513 18 4 I2S function overview 515 18 4 1 I2S block diagram 515 18 4 2 I2S signal description 516 18 4 3 I2S audio standards 516 18 4 4 I2S clock 524 18 4 5 Operation 525 18 4 6 DMA function 529 18 4 7 I2S interrupts 529 18 5 Register definition 531 18 5 1 Control register 0 SPI_CTL0 531 18 5 2 Control register 1 SPI_CTL1 533 18 5 3 Status regist...

Page 12: ...iew 543 19 3 1 Enable OPA 543 19 3 2 Combinatorial work with ADC 543 19 3 3 Use SW when enabled OPA 543 20 Appendix 544 20 1 List of abbreviations used in register 544 20 2 List of terms 544 20 3 Available peripherals 545 21 Revision history 546 ...

Page 13: ...gure 7 1 Block diagram of CRC calculation unit 132 Figure 8 1 Block diagram of DMA 139 Figure 8 2 Handshake mechanism 141 Figure 8 3 DMA interrupt logic 144 Figure 8 4 DMA request mapping 145 Figure 10 1 ADC module block diagram 161 Figure 10 2 Single operation mode 162 Figure 10 3 Continuous operation mode 163 Figure 10 4 Scan operation mode continuous disable 164 Figure 10 5 Scan operation mode ...

Page 14: ... break the break high active 252 Figure 14 20 Counter behavior with CI0FE0 polarity non inverted in mode 2 253 Figure 14 21 Counter behavior with CI0FE0 polarity inverted in mode 2 253 Figure 14 22 Hall sensor is used to BLDC motor 254 Figure 14 23 Hall sensor timing between two timers 255 Figure 14 24 Restart mode 256 Figure 14 25 Pause mode 256 Figure 14 26 Event mode 257 Figure 14 27 Single pul...

Page 15: ...mplementary output with dead time insertion 360 Figure 14 65 Output behavior in response to a break The break high active 361 Figure 14 66 Restart mode 362 Figure 14 67 Pause mode 363 Figure 14 68 Event mode 363 Figure 14 69 Single pulse mode TIMERx_CHxCV 4 TIMERx_CAR 99 364 Figure 14 70 General level4 timer block diagram 387 Figure 14 71 Timing chart of internal clock divided by 1 388 Figure 14 7...

Page 16: ...2 Data validation 469 Figure 17 3 START and STOP signal 469 Figure 17 4 Clock synchronization 470 Figure 17 5 SDA line arbitration 470 Figure 17 6 I2C communication flow with 7 bit address 471 Figure 17 7 I2C communication flow with 10 bit address Master Transmit 471 Figure 17 8 I2C communication flow with 10 bit address Master Receive 471 Figure 17 9 Programming model for slave transmitting 10 bi...

Page 17: ... DTLEN 10 CHLEN 1 CKPL 0 519 Figure 18 29 MSB justified standard timing diagram DTLEN 10 CHLEN 1 CKPL 1 519 Figure 18 30 MSB justified standard timing diagram DTLEN 01 CHLEN 1 CKPL 0 519 Figure 18 31 MSB justified standard timing diagram DTLEN 01 CHLEN 1 CKPL 1 519 Figure 18 32 MSB justified standard timing diagram DTLEN 00 CHLEN 1 CKPL 0 519 Figure 18 33 MSB justified standard timing diagram DTLE...

Page 18: ...iagram DTLEN 10 CHLEN 1 CKPL 1 523 Figure 18 50 PCM standard long frame synchronization mode timing diagram DTLEN 01 CHLEN 1 CKPL 0 523 Figure 18 51 PCM standard long frame synchronization mode timing diagram DTLEN 01 CHLEN 1 CKPL 1 523 Figure 18 52 PCM standard long frame synchronization mode timing diagram DTLEN 00 CHLEN 1 CKPL 0 524 Figure 18 53 PCM standard long frame synchronization mode timi...

Page 19: ... source for ADC 167 Table 10 4 tCONV timings depending on resolution 168 Table 10 5 Maximum output results for N and M combimations grayed values indicates truncation 170 Table 12 1 Min max FWDGT timeout period at 40 kHz IRC40K 189 Table 12 2 Min max timeout value at 72 MHz fPCLK1 196 Table 13 1 RTC power saving mode management 210 Table 13 2 RTC interrupts control 210 Table 14 1 Timers TIMERx are...

Page 20: ...mode 502 Table 18 5 SPI operation modes 502 Table 18 6 SPI interrupt requests 515 Table 18 7 I2S bitrate calculation formulas 524 Table 18 8 Audio sampling frequency calculation formulas 525 Table 18 9 Direction of I2S interface signals for each operation mode 525 Table 18 10 I2S interrupt 530 Table 20 1 List of abbreviations used in register 544 Table 20 2 List of terms 544 Table 21 1 Revision hi...

Page 21: ...to developers including A simple architecture that is easy to learn and program Ultra low power energy efficient operation Excellent code density Deterministic high performance interrupt handling Upward compatibility with Cortex M processor family The processor delivers high energy efficiency through a small but powerful instruction set and extensively optimized design providing high end processin...

Page 22: ...figure The AHB matrix based on AMBA 5 AHB LITE is a multi layer AHB which enables parallel access paths between multiple masters and slaves in the system Two masters on the AHB matrix including AHB bus of the Cortex M23 core and DMA The AHB matrix consists of four slaves including the flash memory controller internal SRAM AHB1 and AHB2 The AHB2 connects with the GPIO ports The AHB1 connects with t...

Page 23: ...IMER15 APB2 F max 72MHz Powered by LDO 1 2V CMP WWDGT APB1 F max 72MHz TIMER5 SPI1 I2C0 RTC FWDGT PMU I2C1 TIMER13 TIMER2 Powered by VDD VDDA IRC40K 40KHz USART1 1 3 Memory map Program memory data memory registers and I O ports are organized within the same linear 4 Gbyte address space which is the maximum address range of the Cortex M23 since it has a 32 bit bus address width Additionally a pre d...

Page 24: ...BFF GPIOC 0x4800 0400 0x4800 07FF GPIOB 0x4800 0000 0x4800 03FF GPIOA AHB1 0x4002 4400 0x47FF FFFF Reserved 0x4002 4000 0x4002 43FF Reserved 0x4002 3400 0x4002 3FFF Reserved 0x4002 3000 0x4002 33FF CRC 0x4002 2400 0x4002 2FFF Reserved 0x4002 2000 0x4002 23FF FMC 0x4002 1400 0x4002 1FFF Reserved 0x4002 1000 0x4002 13FF RCU 0x4002 0400 0x4002 0FFF Reserved 0x4002 0000 0x4002 03FF DMA APB2 0x4001 800...

Page 25: ...000 4800 0x4000 53FF Reserved 0x4000 4400 0x4000 47FF USART1 0x4000 4000 0x4000 43FF Reserved 0x4000 3C00 0x4000 3FFF Reserved 0x4000 3800 0x4000 3BFF SPI1 0x4000 3400 0x4000 37FF Reserved 0x4000 3000 0x4000 33FF FWDGT 0x4000 2C00 0x4000 2FFF WWDGT 0x4000 2800 0x4000 2BFF RTC 0x4000 2400 0x4000 27FF Reserved 0x4000 2000 0x4000 23FF TIMER13 0x4000 1400 0x4000 1FFF Reserved 0x4000 1000 0x4000 13FF T...

Page 26: ...y bits are computed and stored into the SRAM When reading the parity bits are also computed using the stored data in SRAM The computed parity bits are compared with the stored parity bits which are computed during the writing access If they are different the parity check fails Note When enabling the SRAM parity check it is recommended to initialize the whole SRAM memory by software at the beginnin...

Page 27: ... On chip SRAM 1 1 1 The Boot1 value is the opposite of the BOOT1_n value After power on sequence or a system reset the Arm Cortex M23 processor fetches the top of stack value from address 0x0000 0000 and the base address of boot code from 0x0000 0004 in sequence Then it starts executing code from the base address of boot code According to the selected boot source either the main flash memory origi...

Page 28: ...eserved Must be kept at reset value 19 PB9_HCCE PB9 pin high current capability enable When it is set the PB9 pin can be used to control an infrared LED directly 0 High current capability on the PB9 pin is disenabled 1 High current capability on the PB9 pin is enabled and the speed control of the pin is bypassed 18 13 Reserved Must be kept at reset value 12 TIMER16_DMA_RM P Timer 16 DMA request re...

Page 29: ... 12 pin pair on small pin count packages 0 No remap pin pair PA9 10 mapped on the pins 1 Remap pin pair PA11 12 mapped instead of PA9 10 3 2 Reserved Must be kept at reset value 1 0 BOOT_MODE 1 0 Boot mode Refer to Chapter 1 4 Boot configuration for details Bit0 is mapping to the BOOT0 pin the value of bit1 is the opposite of the nBOOT1 option bit value x0 Boot from the Main Flash 01 Boot from the...

Page 30: ... channel 4 9 USART0_TX_DMA_ RMP USART0_TX DMA request remapping enable 0 not remap USART0_TX DMA requests are mapped on DMA channel 1 1 remap USART0_TX DMA requests are mapped on DMA channel 3 8 ADC_DMA_RMP ADC DMA request remapping enable 0 not remap ADC DMA requests are mapped on DMA channel 0 1 remap ADC DMA requests are mapped on DMA channel 1 7 5 Reserved Must be kept at reset value 4 PA11_PA...

Page 31: ... 0 rw rw rw rw Bits Fields Descriptions 31 16 Reserved must be kept at reset value 15 12 EXTI3_SS EXTI 3 sources selection X000 PA3 pin X001 PB3 pin X010 reserved X011 reserved X100 reserved X101 reserved X110 reserved X111 reserved 11 8 EXTI2_SS EXTI 2 sources selection X000 PA2 pin X001 PB2 pin X010 reserved X011 reserved X100 reserved X101 reserved X110 reserved X111 reserved 7 4 EXTI1_SS EXTI ...

Page 32: ...0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXTI7_SS 3 0 EXTI6_SS 3 0 EXTI5_SS 3 0 EXTI4_SS 3 0 rw rw rw rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 12 EXTI7_SS EXTI 7 sources selection X000 PA7 pin X001 PB7 pin X010 reserved X011 reserved X100 reserved X101 PF7 pin X110 reserved X111 reserved 11 8 EXTI6_SS EXTI 6 s...

Page 33: ...reserved X101 reserved X110 reserved X111 reserved 1 5 4 EXTI sources selection register 2 SYSCFG_EXTISS2 For GD32E230xx devices Address offset 0x10 Reset value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXTI11_SS 3 0 EXTI10_SS 3 0 EXTI9_SS 3 0 EXTI8_SS 3 0 rw rw rw rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset valu...

Page 34: ...B9 pin X010 reserved X011 reserved X100 reserved X101 reserved X110 reserved X111 reserved 3 0 EXTI8_SS EXTI 8 sources selection X000 PA8 pin X001 PB8 pin X010 reserved X011 reserved X100 reserved X101 reserved X110 reserved X111 reserved For GD32E231xx devices Address offset 0x10 Reset value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...

Page 35: ...10 pin X010 reserved X011 reserved X100 reserved X101 reserved X110 reserved X111 reserved 7 4 EXTI9_SS EXTI 9 sources selection X000 PA9 pin X001 reserved X010 reserved X011 reserved X100 reserved X101 reserved X110 reserved X111 reserved 3 0 EXTI8_SS EXTI 8 sources selection X000 PA8 pin X001 PB8 pin X010 reserved X011 reserved X100 reserved X101 reserved X110 reserved X111 reserved 1 5 5 EXTI s...

Page 36: ...s selection X000 PA15 pin X001 PB15 pin X010 PC15 pin X011 reserved X100 reserved X101 reserved X110 reserved X111 reserved 11 8 EXTI14_SS EXTI 14 sources selection X000 PA14 pin X001 PB14 pin X010 PC14 pin X011 reserved X100 reserved X101 reserved X110 reserved X111 reserved 7 4 EXTI13_SS EXTI 13 sources selection X000 PA13 pin X001 PB13 pin X010 PC13 pin X011 reserved X100 reserved X101 reserved...

Page 37: ...0 EXTI12_SS 3 0 rw rw rw rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 12 EXTI15_SS EXTI 15 sources selection X000 PA15 pin X001 PB15 pin X010 PC15 pin X011 reserved X100 reserved X101 reserved X110 reserved X111 reserved 11 8 EXTI14_SS EXTI 14 sources selection X000 PA14 pin X001 PB14 pin X010 PC14 pin X011 reserved X100 reserved X101 reserved X110 reserved X111 reserv...

Page 38: ...PARITY_ ERROR_ LOCK LOCK UP_ LOCK rc_w1 rw rw rw Bits Fields Descriptions 31 9 Reserved Must be kept at reset value 8 SRAM_PCEF SRAM parity check error flag This bit is set by hardware when an SRAM parity check error occurs It is cleared by software by writing 1 0 No SRAM parity check error detected 1 SRAM parity check error detected 7 3 Reserved Must be kept at reset value 2 LVD_LOCK LVD lock Thi...

Page 39: ...ster SYSCFG_CPU_IRQ_LAT Address offset 0x100 Reset value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved IRQ_LATENCY rw Bits Fields Descriptions 31 8 Reserved Must be kept at reset value 7 0 IRQ_LATENCY IRQ_LATENCY specifies the minimum number of cycles between an interrupt that becomes pended in the NVIC and the vector fetch for ...

Page 40: ... 31 16 SRAM_DENSITY 15 0 SRAM density The value indicates the on chip SRAM density of the device in Kbytes Example 0x0008 indicates 8 Kbytes 15 0 FLASH_DENSITY 15 0 Flash memory density The value indicates the Flash memory density of the device in Kbytes Example 0x0020 indicates 32 Kbytes 1 6 2 Unique device ID 96 bits Base address 0x1FFF F7AC The value is factory programmed and can never be alter...

Page 41: ...32 r Bits Fields Descriptions 31 0 UNIQUE_ID 63 32 Unique device ID Base address 0x1FFF F7B4 The value is factory programmed and can never be altered by user This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 UNIQUE_ID 95 80 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UNIQUE_ID 79 64 r Bits Fields Descriptions 31 0 UNIQUE_ID 95 64 Unique device ID ...

Page 42: ...lock for user application requirements 1K bytes page size Word or double word programming page erase and mass erase capability Flash read protection to prevent illegal code data access Page erase program protection to prevent unexpected operation 2 3 Function overview 2 3 1 Flash memory architecture The flash memory consists of up to 64 KB main flash organized into 64 pages with 1 KB capacity per ...

Page 43: ...y AHB clock frequency WSCNT configured 24MHz 0 0 wait state added 48MHz 1 1 wait state added 72MHz 2 2 wait state added If system reset occurs the AHB clock frequency is 8MHz and the WSCNT is 0 Note 1 If it is needed to increase the AHB clock frequency First refer to Table 2 2 The relation between WSCNT and AHB clock frequency configure the WSCNT bits according to the target AHB clock frequency Th...

Page 44: ...ations are writing 0x45670123 and 0xCDEF89AB to the FMC_KEY register After the two write operations the LK bit in FMC_CTL register is set to 0 by hardware The software can lock the FMC_CTL again by setting the LK bit in FMC_CTL register to 1 If there is any wrong operations on the FMC_KEY register the LK bit in FMC_CTL register will be set and the FMC_CTL register will be locked then it will gener...

Page 45: ...r is set Note that a correct target page address must be confirmed Or the software may run out of control if the target erase page is being used for fetching codes or accessing data The FMC will not provide any notification when this occurs Additionally the page erase operation will be ignored on protected pages A Flash Operation Error interrupt will be triggered by the FMC if the ERRIE bit in the...

Page 46: ... steps show the mass erase register access sequence Unlock the FMC_CTL register if necessary Check the BUSY bit in FMC_STAT register to confirm that no flash memory operation is in progress BUSY equal to 0 Otherwise wait until the operation has been finished Write the mass erase command into MER bit in FMC_CTL register Send the mass erase command to the FMC by setting the START bit in FMC_CTL regi...

Page 47: ...ramming operation should be 0x0800 0000 The Figure 2 2 Process of the mass erase operation indicates the mass erase operation flow Figure 2 2 Process of the mass erase operation Set the MER bit Is the LK bit 0 Send the command to FMC by setting START bit Start Yes No Unlock the FMC_CTL Is the BUSY bit 0 Yes No Is the BUSY bit 0 Yes No Finish 2 3 6 Main flash programming The FMC provides a 32 bit w...

Page 48: ...d must double word alignment For less program time suggest the DBUS program use 32 bit set the PGW to 1 if the data to be programed is double word alignment or set PGW to 0 if the data to be programed is word alignment Wait until all the operations have been completed by checking the value of the BUSY bit in FMC_STAT register Read and verify the flash memory if required using a DBUS access When th...

Page 49: ...s 32bits by setting the PGW bit in the FMC_WS register the data is not program to the flash memory without any notice In these conditions a flash operation error interrupt will be triggered by the FMC if the ERRIE bit in the FMC_CTL register is set The software can check the PGERR bit PGAERR bit or WPERR bit in the FMC_STAT register to detect which condition occurred in the interrupt handler The F...

Page 50: ...ions have been completed by checking the value of the BUSY bit in FMC_STAT register Read and verify the flash memory if required using a DBUS access When the operation is executed successfully an interrupt will be triggered by FMC if the ENDIE bit in the FMC_CTL register is set and the ENDF in FMC_STAT register is set The end of this operation is indicated by the ENDF bit in the FMC_STAT register ...

Page 51: ... opposite of option bytes When option bytes reload if the option complement bytes and option bytes does not match the OBERR bit in FMC_OBSTAT register is set and the option byte is set to 0xFF The Table 2 3 Option byte is the detail of option bytes Table 2 3 Option byte Address Name Description 0x1fff f800 OB_SPC option byte Security Protection Code 0xA5 No protection any value except 0xA5 or 0xCC...

Page 52: ...er will then be set by the FMC If the WPERR bit is set and the ERRIE bit is also set to 1 to enable the corresponding interrupt then the flash operation error interrupt will be triggered by the FMC to get the attention of the CPU The page protection function can be individually enabled by configuring the OB_WP 15 0 bit field to 0 in the option byte If a page erase operation is executed on the Opti...

Page 53: ...boot from SRAM or boot from boot loader mode the PGERR bit in FMC_STAT register will be set At protection level low option bytes block are accessible by all operations If program back to no protection level by setting OB_SPC byte and its complement value to 0xA55A a mass erase for main flash will be performed Protection level high when set OB_SPC byte and its complement value to 0xCC33 protection ...

Page 54: ...ved Must be kept at reset value 15 PGW Program width to flash memory 0 32 bit program width to flash memory 1 64 bit program width to flash memory 14 5 Reserved Must be kept at reset value 4 PFEN Pre fetch enable 0 Pre fetch disable 1 Pre fetch enable 3 Reserved Must be kept at reset value 2 0 WSCNT 2 0 Wait state counter register These bits set and reset by software 000 0 wait state added 001 1 w...

Page 55: ...ord 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 OBKEY 31 16 w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OBKEY 15 0 w Bits Fields Descriptions 31 0 OBKEY 31 0 FMC_CTL option byte operation unlock registers These bits are only be written by software Write OBKEY 31 0 with key to unlock option byte command in FMC_CTL register 2 4 4 Status register FMC_STAT Address offset 0x0C Reset value 0x0000...

Page 56: ... is set by hardware The software can clear it by writing 1 1 Reserved Must be kept at reset value 0 BUSY The flash busy bit When the operation is in progress this bit is set to 1 When the operation is end or an error generated this bit is clear to 0 2 4 5 Control register FMC_CTL Address offset 0x10 Reset value 0x0000 0080 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 ...

Page 57: ...gister This bit can be set by software 6 START Send erase command to FMC bit This bit is set by software to send erase command to FMC This bit is cleared by hardware when the BUSY bit is cleared 5 OBER Option byte erase command bit This bit is set or cleared by software 0 No effect 1 Option byte erase command 4 OBPG Option byte program command bit This bit is set or cleared by software 0 No effect...

Page 58: ...ash erase command 2 4 7 Option byte status register FMC_OBSTAT Address offset 0x1C Reset value 0xXXXX XX0X This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 OB_DATA 15 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OB_USER 7 0 Reserved PLEVEL 1 0 OBERR r r r Bits Fields Descriptions 31 16 OB_DATA 15 0 Store OB_DATA 15 0 of option byte block after system res...

Page 59: ...elds Descriptions 31 16 Reserved Must be kept at reset value 15 0 OB_WP 15 0 Store OB_WP 15 0 of option byte block after system reset 0 Protection active 1 Unprotected 2 4 9 Product ID register FMC_PID Address offset 0x100 Reset value 0xXXXX XXXX This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PID 31 16 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PID 15 ...

Page 60: ...kup domain as is shown in Figure 3 1 Power supply overview The power of the VDD domain is supplied directly by VDD An embedded LDO in the VDD VDDA domain is used to supply the 1 2V domain power Backup domain is powered from the main VDD supply 3 2 Characteristics Three power domains VBAK VDD VDDA and 1 2V power domains Three power saving modes Sleep Deep sleep and Standby modes Internal Voltage re...

Page 61: ...rces include the Backup domain power on reset BPOR and the Backup Domain software reset The BPOR signal forces the device to stay in the reset mode until VBAK is completely powered up Also the application software can trigger the Backup domain software reset by setting the BKPRST bit in the RCU_BDCTL register to reset the Backup domain The clock source of the Real Time Clock RTC circuit can be der...

Page 62: ...ector etc VDD domain The LDO which is implemented to supply power for the 1 2V domain is always enabled after reset It can be configured to operate in three different status including in the Sleep mode full power on in the Deep sleep mode on or low power and in the Standby mode power off The POR PDR circuit is implemented to detect VDD VDDA and generate the power reset signal which resets the whol...

Page 63: ..._CS indicates if VDD VDDA is higher or lower than the LVD threshold This event is internally connected to the EXTI line 16 and can generate an interrupt if it is enabled through the EXTI registers Figure 3 3 Waveform of the LVD threshold shows the relationship between the LVD threshold and the LVD output LVD interrupt signal depends on EXTI line 16 rising or falling edge configuration The followin...

Page 64: ...ll power domains are active Users can achieve lower power consumption through slowing down the system clocks HCLK PCLK1 PCLK2 or gating the clocks of the unused peripherals or configuring the LDO output voltage by LDOVS bits in PMU_CTL register The LDOVS bits should be configured only when the PLL is off Besides three power saving modes are provided to achieve even lower power consumption they are...

Page 65: ...lags must be reset refer to Table 5 3 EXTI source If not the program will skip the entry process of Deep sleep mode to continue to execute the following procedure Standby mode The Standby mode is based on the SLEEPDEEP mode of the Cortex M23 too In Standby mode the whole 1 2V domain is power off the LDO is shut down and all of IRC8M IRC28M HXTAL and PLL are disabled Before entering the Standby mod...

Page 66: ...upt when SEVONPEND is 1 for WFE Any interrupt from EXTI lines for WFI Any event or interrupt when SEVONPEND is 1 from EXTI for WFE 1 NRST pin 2 WKUP pins 3 FWDGT reset 4 RTC Wakeup Latency None IRC8M wakeup time LDO wakeup time added if LDO is in low power mode Power on sequence Note In Standby mode all I Os are in high impedance state except NRST pin PC13 pin when configured for RTC function PC14...

Page 67: ... output voltage select These bits are set by software when the main PLL closed 00 Reserved LDO output voltage high mode 01 LDO output voltage high mode 1x LDO output voltage low mode 13 9 Reserved Must be kept at reset value 8 BKPWEN Backup Domain Write Enable 0 Disable write access to the registers in Backup domain 1 Enable write access to the registers in Backup domain After reset any write acce...

Page 68: ...s may work with the IRC8M clock in the Deep sleep mode In this case the LDO automatically switches from the low power mode to the normal mode and remains in this mode until the peripheral stop working 3 4 2 Control and status register PMU_CS For GD32E230xx devices Address offset 0x04 Reset value 0x0000 0000 not reset by wakeup from Standby mode This register can be accessed by half word 16 bit or ...

Page 69: ...pin1 is internally configured to input pull down mode And set this bit will trigger a wakeup event when the input is already high 8 WUPEN0 WKUP Pin 0 PA0 Enable 0 Disable WKUP pin0 function 1 Enable WKUP pin0 function If WUPEN0 is set before entering the power saving mode a rising edge on the WKUP pin0 wakes up the system from the power saving mode As the WKUP pin0 is active high the WKUP pin0 is ...

Page 70: ... power saving mode As the WKUP pin6 is active high the WKUP pin6 is internally configured to input pull down mode And set this bit will trigger a wakeup event when the input is already high 13 WUPEN5 WKUP Pin5 PB5 Enable 0 Disable WKUP pin5 function 1 Enable WKUP pin5 function If WUPEN5 is set before entering the power saving mode a rising edge on the WKUP pin5 wakes up the system from the power s...

Page 71: ...LVD threshold Note The LVD function is stopped in Standby mode 1 STBF Standby Flag 0 The device has not entered the Standby mode 1 The device has been in the Standby mode This bit is cleared only by a POR PDR or by setting the STBRST bit in the PMU_CTL register 0 WUF Wakeup Flag 0 No wakeup event has been received 1 Wakeup event occurred from the WKUP pin or the RTC wakeup event including RTC Tamp...

Page 72: ...power on and power down reset POR PDR reset or by the internal reset generator when exiting Standby mode The power reset sets all registers to their reset values except the backup domain The power reset which active signal is low will be de asserted when the internal LDO voltage regulator is ready to provide 1 2V power for GD32E23x series The reset service routine vector is fixed at address 0x0000...

Page 73: ...set VDD power on 4 2 Clock control unit CCTL 4 2 1 Overview The clock control unit provides a range of frequencies and clock functions These include an Internal 8 MHz RC oscillator IRC8M an Internal 28 MHz RC oscillator IRC28M a High speed crystal oscillator HXTAL Internal 40KHz RC oscillator IRC40K a Low speed crystal oscillator LXTAL a Phase Lock Loop PLL a HXTAL clock monitor clock prescalers c...

Page 74: ...if APB1 prescaler 1 1 else APB1 prescaler 2 TIMER0 14 15 16 if APB2 prescaler 1 1 else APB2 prescaler 2 The frequency of AHB APB2 and the APB1 domains can be configured by each prescaler The maximum frequency of the AHB APB2 and APB1 domains is 72 MHz 72 MHz 72 MHz The Cortex System Timer SysTick external clock is clocked with the AHB clock HCLK divided by 8 The systick can work either with this c...

Page 75: ...per oscillation Figure 4 3 HXTAL clock source OSCIN OSCOUT C1 C2 Crystal The HXTAL crystal oscillator can be switched on or off using the HXTALEN bit in the control register 0 RCU_CTL0 The HXTALSTB flag in control register 0 RCU_CTL0 indicates if the high speed external crystal oscillator is stable When the HXTAL is powered up it will not be released for use until this HXTALSTB bit is set by the h...

Page 76: ...PLL can provide 16 72 MHz clock output which is 2 32 multiples of a fundamental reference frequency of 4 32 MHz The PLL can be switched on or off by using the PLLEN bit in the Control register 0 RCU_CTL0 The PLLSTB flag in the Control register 0 RCU_CTL0 will indicate if the PLL clock is stable An interrupt can be generated if the related interrupt enable bit PLLSTBIE in the Interrupt register RCU...

Page 77: ...e using the original clock source until the target clock source is stable When a clock source is used directly by the CK_SYS or the PLL it is not possible to stop it HXTAL Clock Monitor CKM The HXTAL clock monitor function is enabled by the HXTAL clock monitor enable bit CKMEN in the control register 0 RCU_CTL0 This function should be enabled after the HXTAL start up delay and disabled when the HX...

Page 78: ...ock is enable If the USART0 clock is selected IRC8M clock in Deep sleep mode they have capable of open IRC8M clock or close IRC8M clock which used to the USART0 to wake up the Deep sleep mode Voltage control The core domain voltage in Deep sleep mode can be controlled by DSLPVS 1 0 bits in the Deep sleep mode voltage register RCU_DSV Table 4 2 Core domain voltage selected in Deep sleep mode DSLPVS...

Page 79: ... is stable 24 PLLEN PLL enable Set and reset by software This bit cannot be reset if the PLL clock is used as the system clock Reset by hardware when entering Deep sleep or Standby mode 0 PLL is switched off 1 PLL is switched on 23 20 Reserved Must be kept at reset value 19 CKMEN HXTAL clock monitor enable 0 Disable the external 4 32 MHz crystal oscillator HXTAL clock monitor 1 Enable the external...

Page 80: ...or calibration value register These bits are load automatically at power on 7 3 IRC8MADJ 4 0 Internal 8M RC oscillator clock trim adjust value These bits are set by software The trimming value is there bits IRC8MADJ added to the IRC8MCALIB 7 0 bits The trimming value should trim the IRC8M to 8 MHz 1 2 Reserved Must be kept at reset value 1 IRC8MSTB IRC8M high speed internal oscillator stabilizatio...

Page 81: ...UT is divided by 8 100 The CK_OUT is divided by 16 101 The CK_OUT is divided by 32 110 The CK_OUT is divided by 64 111 The CK_OUT is divided by 128 27 PLLMF 4 Bit 4 of PLLMF register see bits 21 18 of RCU_CFG0 26 24 CKOUTSEL 2 0 CK_OUT clock source selection Set and reset by software 000 No clock selected 001 Internal 28M RC oscillator clock selected 010 Internal 40K RC oscillator clock selected 0...

Page 82: ...L source clock x 25 11001 PLL source clock x 26 11010 PLL source clock x 27 11011 PLL source clock x 28 11100 PLL source clock x 29 11101 PLL source clock x 30 11110 PLL source clock x 31 11111 PLL source clock x 32 Note The PLL output frequency must not exceed 72 MHz 17 PLLPREDV HXTAL divider for PLL source clock selection This bit is the same bit as bit PREDV 0 from RCU_CFG1 Refer to RCU_CFG1 PR...

Page 83: ... to control the APB1 clock division ratio 0xx CK_AHB selected 100 CK_AHB 2 selected 101 CK_AHB 4 selected 110 CK_AHB 8 selected 111 CK_AHB 16 selected 7 4 AHBPSC 3 0 AHB prescaler selection Set and reset by software to control the AHB clock division ratio 0xxx CK_SYS selected 1000 CK_SYS 2 selected 1001 CK_SYS 4 selected 1010 CK_SYS 8 selected 1011 CK_SYS 16 selected 1100 CK_SYS 64 selected 1101 C...

Page 84: ...23 22 21 20 19 18 17 16 Reserved CKMIC Reserved IRC28M STBIC PLL STBIC HXTAL STBIC IRC8M STBIC LXTAL STBIC IRC40K STBIC w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved IRC28M STBIE PLL STBIE HXTAL STBIE IRC8M STBIE LXTAL STBIE IRC40K STBIE CKMIF Reserved IRC28M STBIF PLL STBIF HXTAL STBIF IRC8M STBIF LXTAL STBIF IRC40K STBIF rw rw rw rw rw rw r r r r r r r Bits Fields Descriptions 31 ...

Page 85: ...ble the IRC28M stabilization interrupt 1 Enable the IRC28M stabilization interrupt 12 PLLSTBIE PLL stabilization interrupt enable Set and reset by software to enable disable the PLL stabilization interrupt 0 Disable the PLL stabilization interrupt 1 Enable the PLL stabilization interrupt 11 HXTALSTBIE HXTAL stabilization interrupt enable Set and reset by software to enable disable the HXTAL stabil...

Page 86: ... stabilization interrupt flag Set by hardware when the External 4 32 MHz crystal oscillator clock is stable and the HXTALSTBIE bit is set Reset by software when setting the HXTALSTBIC bit 0 No HXTAL stabilization interrupt generated 1 HXTAL stabilization interrupt generated 2 IRC8MSTBIF IRC8M stabilization interrupt flag Set by hardware when the Internal 8 MHz RC oscillator clock is stable and the...

Page 87: ...RST TIMER0 RST Reserved ADC RST Reserved CFGCMP RST rw rw rw rw rw Bits Fields Descriptions 31 19 Reserved Must be kept at reset value 18 TIMER16RST TIMER16 reset This bit is set and reset by software 0 No reset 1 Reset the TIMER16 17 TIMER15RST TIMER15 reset This bit is set and reset by software 0 No reset 1 Reset the TIMER15 16 TIMER14RST TIMER14 reset This bit is set and reset by software 0 No ...

Page 88: ...5 APB1 reset register RCU_APB1RST Address offset 0x10 Reset value 0x0000 0000 This register can be accessed by byte 8 bit half word 16 bit and word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved PMU RST Reserved I2C1 RST I2C0 RST Reserved USART1 RST Reserve rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SPI1 RST Reserved WWDGT RST Reserved TIMER13 RST Reserved TIMER5 R...

Page 89: ...reset by software 0 No reset 1 Reset SPI1 13 12 Reserved Must be kept at reset value 11 WWDGTRST Window watchdog timer reset This bit is set and reset by software 0 No reset 1 Reset window watchdog timer 10 9 Reserved Must be kept at reset value 8 TIMER13RST TIMER13 timer reset This bit is set and reset by software 0 No reset 1 Reset TIMER13 TIMER 7 5 Reserved Must be kept at reset value 4 TIMER5R...

Page 90: ... Reserved Must be kept at reset value 22 PFEN GPIO port F clock enable This bit is set and reset by software 0 Disabled GPIO port F clock 1 Enabled GPIO port F clock 21 20 Reserved Must be kept at reset value 19 PCEN GPIO port C clock enable This bit is set and reset by software 0 Disabled GPIO port C clock 1 Enabled GPIO port C clock 18 PBEN GPIO port B clock enable This bit is set and reset by s...

Page 91: ... clock during Sleep mode 1 Reserved Must be kept at reset value 0 DMAEN DMA clock enable This bit is set and reset by software 0 Disabled DMA clock 1 Enabled DMA clock 4 3 7 APB2 enable register RCU_APB2EN Address offset 0x18 Reset value 0x0000 0000 This register can be accessed by byte 8 bit half word 16 bit and word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved DBGMCU EN Reserv...

Page 92: ...EN USART0 clock enable This bit is set and reset by software 0 Disabled USART0 clock 1 Enabled USART0 clock 13 Reserved Must be kept at reset value 12 SPI0EN SPI0 clock enable This bit is set and reset by software 0 Disabled SPI0 clock 1 Enabled SPI0 clock 11 TIMER0EN TIMER0 timer clock enable This bit is set and reset by software 0 Disabled TIMER0 timer clock 1 Enabled TIMER0 timer clock 10 Reser...

Page 93: ...w rw rw Bits Fields Descriptions 31 29 Reserved Must be kept at reset value 28 PMUEN Power interface clock enable This bit is set and reset by software 0 Disabled Power interface clock 1 Enabled Power interface clock 27 23 Reserved Must be kept at reset value 22 I2C1EN I2C1 clock enable This bit is set and reset by software 0 Disabled I2C1 clock 1 Enabled I2C1 clock 21 I2C0EN I2C0 clock enable Thi...

Page 94: ...isabled TIMER5 timer clock 1 Enabled TIMER5 timer clock 3 2 Reserved Must be kept at reset value 1 TIMER2EN TIMER2 timer clock enable This bit is set and reset by software 0 Disabled TIMER2 timer clock 1 Enabled TIMER2 timer clock 0 Reserved Must be kept at reset value 4 3 9 Backup domain control register RCU_BDCTL Address offset 0x20 Reset value 0x0000 0018 reset by backup domain reset This regis...

Page 95: ... as RTC source clock 10 CK_IRC40K selected as RTC source clock 11 CK_HXTAL 32 selected as RTC source clock 7 5 Reserved Must be kept at reset value 4 3 LXTALDRI 1 0 LXTAL drive capability Set and reset by software Backup domain reset reset this value 00 lower driving capability 01 medium low driving capability 10 medium high driving capability 11 higher driving capability reset value Note The LXTA...

Page 96: ...are when Deep sleep standby reset generated Reset by writing 1 to the RSTFC bit 0 No Low power management reset generated 1 Low power management reset generated 30 WWDGTRSTF Window watchdog timer reset flag Set by hardware when a window watchdog timer reset generated Reset by writing 1 to the RSTFC bit 0 No window watchdog reset generated 1 Window watchdog reset generated 29 FWDGTRSTF Free Watchdo...

Page 97: ...is set by software to clear all reset flags 0 Not clear reset flags 1 Clear reset flags 23 V12RSTF V12 domain Power reset flag Set by hardware when a V12 domain power reset generated Reset by writing 1 to the RSTFC bit 0 No V12 domain power reset generated 1 V12 domain power reset generated 22 2 Reserved Must be kept at reset value 1 IRC40KSTB IRC40K stabilization Set by hardware to indicate if th...

Page 98: ...d reset by software 0 No reset GPIO port C 1 Reset GPIO port C 18 PBRST GPIO port B reset This bit is set and reset by software 0 No reset GPIO port B 1 Reset GPIO port B 17 PARST GPIO port A reset This bit is set and reset by software 0 No reset GPIO port A 1 Reset GPIO port A 16 0 Reserved Must be kept at reset value 4 3 12 Configuration register 1 RCU_CFG1 Address offset 0x2C Reset value 0x0000...

Page 99: ...input to PLL divided by 7 0111 input to PLL divided by 8 1000 input to PLL divided by 9 1001 input to PLL divided by 10 1010 input to PLL divided by 11 1011 input to PLL divided by 12 1100 input to PLL divided by 13 1101 input to PLL divided by 14 1110 input to PLL divided by 15 1111 input to PLL divided by 16 4 3 13 Configuration register 2 RCU_CFG2 Address offset 0x30 Reset value 0x0000 0000 Thi...

Page 100: ...3 14 Control register 1 RCU_CTL1 Address offset 0x34 Reset value 0x0000 XX80 where X is undefined This register can be accessed by byte 8 bit half word 16 bit and word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IRC28MCALIB 7 0 IRC28MADJ 4 0 Reserved IRC28MS TB IRC28ME N r rw r rw Bits Fields Descriptions 31 16 Reserved Must be kept at rese...

Page 101: ...rd 16 bit and word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 KEY 31 16 w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 KEY 15 0 w Bits Fields Descriptions 31 0 KEY 31 0 The key of RCU_DSV register These bits are written only by software and read as 0 Only after write 0x1A2B3C4D to the RCU_VKEY the RCU_DSV register can be written 4 3 16 Deep sleep mode voltage register RCU_DSV Offset 0x134 Res...

Page 102: ...These bits is set and reset by software 00 The core voltage is 1 0V in Deep sleep mode 01 The core voltage is 0 9V in Deep sleep mode 10 The core voltage is 0 8V in Deep sleep mode 11 The core voltage is 1 2V in Deep sleep mode ...

Page 103: ...ral interrupts for GD32E23x series 2 bits interrupt priority configuration 4 priority levels Efficient interrupt processing Support exception pre emption and tail chaining Wake up system from power saving mode Up to 21 independent edge detectors in EXTI Three trigger types rising falling and both edges Software interrupt or event trigger Trigger sources configurable 5 3 Interrupts function overvie...

Page 104: ... vector table Interrupt Number Vector Number Peripheral Interrupt Description Vector Address IRQ 0 16 Window watchdog interrupt 0x0000_0040 IRQ 1 17 LVD through EXTI Line detection interrupt 0x0000_0044 IRQ 2 18 RTC global interrupt 0x0000_0048 IRQ 3 19 FMC global interrupt 0x0000_004C IRQ 4 20 RCU global interrupt 0x0000_0050 IRQ 5 21 EXTI Line0 1 interrupt 0x0000_0054 IRQ 6 22 EXTI Line2 3 inter...

Page 105: ...l interrupt 0x0000_00AC IRQ 28 44 USART1 global interrupt 0x0000_00B0 IRQ 29 45 Reserved 0x0000_00B4 IRQ 30 46 Reserved 0x0000_00B8 IRQ 31 47 Reserved 0x0000_00BC IRQ 32 48 I2C0 error interrupt 0x0000_00C0 IRQ 33 49 Reserved 0x0000_00C4 IRQ 34 50 I2C1 error interrupt 0x0000_00C8 IRQ 35 51 Reserved 0x0000_00CC IRQ 36 52 Reserved 0x0000_00D0 IRQ 37 53 Reserved 0x0000_00D4 IRQ 38 54 Reserved 0x0000_0...

Page 106: ...nd 5 lines from internal modules including LVD RTC USART and CMP for GD32E23x series All GPIO pins can be selected as an EXTI trigger source by configuring SYSCFG_EXTISSx registers in SYSCFG module please refer to System configuration registers SYSCFG section for detail EXTI can provide not only interrupts but also event signals to the processor The Cortex M23 processor fully implements the Wait F...

Page 107: ...PB11 12 PA12 PB12 13 PA13 PB13 PC13 14 PA14 PB14 PC14 15 PA15 PB15 PC15 16 LVD 17 RTC Alarm 18 Reserved 19 RTC Tamper and Timestamp 20 Reserved 21 CMP output 22 Reserved 23 Reserved 24 Reserved 25 USART0 Wakeup 26 Reserved 27 Reserved For GD32E231xx devices EXTI Line Number Source 0 PA0 PB0 PF0 1 PA1 PB1 PF1 2 PA2 PB2 3 PA3 PB3 4 PA4 PB4 5 PA5 PB5 6 PA6 PB6 PF6 7 PA7 PB7 PF7 8 PA8 PB8 ...

Page 108: ...A9 10 PA10 PB10 11 PA11 PB11 12 PA12 PB12 13 PA13 PB13 14 PA14 PB14 PC14 15 PA15 PB15 PC15 16 LVD 17 RTC Alarm 18 Reserved 19 RTC Tamper and Timestamp 20 Reserved 21 CMP output 22 Reserved 23 Reserved 24 Reserved 25 USART0 Wakeup 26 Reserved 27 Reserved ...

Page 109: ...Bits Fields Descriptions 31 28 Reserved Must be kept at reset value 27 0 INTENx Interrupt enable bit x x 0 27 0 Interrupt from Linex is disabled 1 Interrupt from Linex is enabled 5 6 2 Event enable register EXTI_EVEN Address offset 0x04 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved EVEN27 EVEN26 EVEN25 EVEN24 EVEN23...

Page 110: ...ex is invalid 1 Rising edge of Linex is valid as an interrupt event request 20 Reserved Must be kept at reset value 19 RTENx Rising edge trigger enable x 19 0 Rising edge of Linex is invalid 1 Rising edge of Linex is valid as an interrupt event request 18 Reserved Must be kept at reset value 17 0 RTENx Rising edge trigger enable x 0 17 0 Rising edge of Linex is invalid 1 Rising edge of Linex is va...

Page 111: ...upt event register EXTI_SWIEV Address offset 0x10 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved SWIEV21 Reserved SWIEV19 Reserved SWIEV17 SWIEV16 rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SWIEV15 SWIEV14 SWIEV13 SWIEV12 SWIEV11 SWIEV10 SWIEV9 SWIEV8 SWIEV7 SWIEV6 SWIEV5 SWIEV4 SWIEV3 SWIEV2 SWIEV1 SWIEV0 rw ...

Page 112: ...D13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 Bits Fields Descriptions 31 22 Reserved Must be kept at reset value 21 PDx Interrupt pending status x 21 0 EXTI Linex is not triggered 1 EXTI Linex is triggered This bit is cleared to 0 by writing 1 to it 20 Reserved Must be kept at reset value ...

Page 113: ... open drain input peripheral alternate function or analog mode Each GPIO pin can be configured as pull up pull down or floating All GPIOs are high current capable except for analog mode 6 2 Characteristics Input output direction control Schmitt trigger input function enable control Each pin weak pull up pull down function Output push pull open drain enable control Output set reset control Output d...

Page 114: ...sh pull Floating 10 0 00 Pull up 01 Pull down 10 Open drain Floating 1 00 Pull up 01 Pull down 10 ANALOG X X 11 X XX Figure 6 1 Basic structure of of a general pupose I O shows the basic structure of an I O Port bit Figure 6 1 Basic structure of of a general pupose I O Read Vss Output Control Register Write Read Write Alternate Function Output Alternate Function Input Input driver Output driver Re...

Page 115: ...y programming 1 to the bit operate register GPIOx_BOP or for clearing only GPIOx_BC or for toggle only GPIOx_TG The other bits will not be affected 6 3 2 Alternate functions AF When the port is configured as AFIO set CTLy bits to 0b10 which is in GPIOx_CTL registers the port is used as peripheral alternate functions Each port has sixteen alternate functions can be configured by GPIO alternate func...

Page 116: ... 1 in the output control register Push Pull mode The pad outputs 0 when a 0 in the output control register while the pad outputs 1 when a 1 in the output control register A read access to the port output control register gets the last written value A read access to the port input status register gets the I O state Figure 6 3 Basic structure of Output configuration shows the output configuration of...

Page 117: ...er is enabled in open drain or push pull configuration The output buffer is driven by the peripheral The schmitt trigger input is activated The weak pull up and pull down resistors could be chosen The data present on the I O pin is sampled into the port input status register every AHB clock cycle A read access to the port input status register gets the I O state in Open Drain mode A read access to...

Page 118: ...cking register GPIOx_LOCK When the special LOCK sequence has been applied on a port bit it is no longer able to modify the value of the port bit until the next reset It should be recommended to be used in the configuration of driving a power module 6 3 9 GPIO single cycle toggle function GPIO could toggle the I O output level in single AHB cycle by writing 1 to the corresponding bit of GPIOx_TG re...

Page 119: ...0 CTL2 1 0 CTL1 1 0 CTL0 1 0 rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 30 CTL15 1 0 Pin 15 configuration bits These bits are set and cleared by software Refer to CTL0 1 0 description 29 28 CTL14 1 0 Pin 14 configuration bits These bits are set and cleared by software Refer to CTL0 1 0 description 27 26 CTL13 1 0 Pin 13 configuration bits These bits are set and cleared by software Refer t...

Page 120: ...4 configuration bits These bits are set and cleared by software Refer to CTL0 1 0 description 7 6 CTL3 1 0 Pin 3 configuration bits These bits are set and cleared by software Refer to CTL0 1 0 description 5 4 CTL2 1 0 Pin 2 configuration bits These bits are set and cleared by software Refer to CTL0 1 0 description 3 2 CTL1 1 0 Pin 1 configuration bits These bits are set and cleared by software Ref...

Page 121: ...de bit These bits are set and cleared by software Refer to OM0 description 12 OM12 Pin 12 output mode bit These bits are set and cleared by software Refer to OM0 description 11 OM11 Pin 11 output mode bit These bits are set and cleared by software Refer to OM0 description 10 OM10 Pin 10 output mode bit These bits are set and cleared by software Refer to OM0 description 9 OM9 Pin 9 output mode bit ...

Page 122: ... 0 Output push pull mode reset value 1 Output open drain mode 6 4 3 Port output speed register GPIOx_OSPD x A C F Address offset 0x08 Reset value 0x0C00 0000 for port A 0x0000 0000 for others This register can be accessed by byte 8 bit half word 16 bit and word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 OSPD15 1 0 OSPD14 1 0 OSPD13 1 0 OSPD12 1 0 OSPD11 1 0 OSPD10 1 0 OSPD9 1 0 OSPD8 1...

Page 123: ...0 1 0 description 17 16 OSPD8 1 0 Pin 8 output max speed bits These bits are set and cleared by software Refer to OSPD0 1 0 description 15 14 OSPD7 1 0 Pin 7 output max speed bits These bits are set and cleared by software Refer to OSPD0 1 0 description 13 12 OSPD6 1 0 Pin 6 output max speed bits These bits are set and cleared by software Refer to OSPD0 1 0 description 11 10 OSPD5 1 0 Pin 5 output...

Page 124: ...rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PUD7 1 0 PUD6 1 0 PUD5 1 0 PUD4 1 0 PUD3 1 0 PUD2 1 0 PUD1 1 0 PUD0 1 0 rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 30 PUD15 1 0 Pin 15 pull up or pull down bits These bits are set and cleared by software Refer to PUD0 1 0 description 29 28 PUD14 1 0 Pin 14 pull up or pull down bits These bits are set and cleared by software Refer to PUD0 1 0 descri...

Page 125: ...et and cleared by software Refer to PUD0 1 0 description 9 8 PUD4 1 0 Pin 4 pull up or pull down bits These bits are set and cleared by software Refer to PUD0 1 0 description 7 6 PUD3 1 0 Pin 3 pull up or pull down bits These bits are set and cleared by software Refer to PUD0 1 0 description 5 4 PUD2 1 0 Pin 2 pull up or pull down bits These bits are set and cleared by software Refer to PUD0 1 0 d...

Page 126: ...4 6 Port output control register GPIOx_OCTL x A C F Address offset 0x14 Reset value 0x0000 0000 This register can be accessed by byte 8 bit half word 16 bit and word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OCTL15 OCTL14 OCTL13 OCTL12 OCTL11 OCTL10 OCTL9 OCTL8 OCTL7 OCTL6 OCTL5 OCTL4 OCTL3 OCTL2 OCTL1 OCTL0 rw rw rw rw rw rw rw rw rw rw ...

Page 127: ...rresponding OCTLy bit 6 4 8 Port configuration lock register GPIOx_LOCK x A B Address offset 0x1C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved LKK rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LK15 LK14 LK13 LK12 LK11 LK10 LK9 LK8 LK7 LK6 LK5 LK4 LK3 LK2 LK1 LK0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits Field...

Page 128: ...ware Refer to SEL0 3 0 description 27 24 SEL6 3 0 Pin 6 alternate function selected These bits are set and cleared by software Refer to SEL0 3 0 description 23 20 SEL5 3 0 Pin 5 alternate function selected These bits are set and cleared by software Refer to SEL0 3 0 description 19 16 SEL4 3 0 Pin 4 alternate function selected These bits are set and cleared by software Refer to SEL0 3 0 description...

Page 129: ...13 3 0 SEL12 3 0 rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SEL11 3 0 SEL10 3 0 SEL9 3 0 SEL8 3 0 rw rw rw rw Bits Fields Descriptions 31 28 SEL15 3 0 Pin 15 alternate function selected These bits are set and cleared by software Refer to SEL8 3 0 description 27 24 SEL14 3 0 Pin 14 alternate function selected These bits are set and cleared by software Refer to SEL8 3 0 description 23 20 SEL1...

Page 130: ...ted Port A B only 0111 AF7 selected Port A B only 1000 1111 Reserved 6 4 11 Bit clear register GPIOx_BC x A C F Address offset 0x28 Reset value 0x0000 0000 This register can be accessed by byte 8 bit half word 16 bit and word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CR15 CR14 CR13 CR12 CR11 CR10 CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 w ...

Page 131: ... Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TG15 TG14 TG13 TG12 TG11 TG10 TG9 TG8 TG7 TG6 TG5 TG4 TG3 TG2 TG1 TG0 w w w w w w w w w w w w w w w w Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 TGy Port toggle bit y y 0 15 These bits are set and cleared by software 0 No action on the corresponding OCTLy bit 1 Toggle the corresponding OCTLy bit ...

Page 132: ... supports 7 8 16 32 size bit Different input size for different calculation time 1 2 4 cycle for 7 8 16 32 bits Input and output data can be reversed User configurable polynomial size User configurable initial value after CRC reset Free 8 bit register is unrelated to calculation and can be used for any other goals by any other peripheral devices Figure 7 1 Block diagram of CRC calculation unit AHB...

Page 133: ...r input data 3 reverse types can be selected Original data is 0x3456CDEF 1 byte reverse 32 bit data is divided into 4 groups and reverse implement in group inside Reversed data 0x2C6AB3F7 2 half word reverse 32 bit data is divided into 2 groups and reverse implement in group inside Reversed data 0x6A2CF7B3 3 word reverse 32 bit data is divided into 1 groups and reverse implement in group inside Re...

Page 134: ...GD32E23x User Manual 134 is unavailable It is strongly recommend resetting the CRC management unit after change the PS 1 0 bits or polynomial ...

Page 135: ...sult bits Software writes and reads This register is used to calculate new data and the register can be written the new data directly Write value cannot be read because the read value is the previous CRC calculation result 7 4 2 Free data register CRC_FDATA Address offset 0x04 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Re...

Page 136: ...t reset value 7 REV_O Reverse output data value in bit order 0 Not bit reversed for output data 1 Bit reversed for output data 6 5 REV_I 1 0 Reverse type for input data 0 Dot not use reverse for input data 1 Reverse input data with every 8 bit length 2 Reverse input data with every 16 bit length 3 Reverse input data with whole 32 bit length 4 3 PS 1 0 Size of polynomial 0 32 bit 1 16 bit POLY 15 0...

Page 137: ...riptions 31 0 IDATA 31 0 Configurable initial CRC data value When RST bit in CRC_CTL asserted CRC_DATA will be programmed to this value 7 4 5 Polynomial register CRC_POLY Address offset 0x14 Reset value 0x04C1 1DB7 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 POLY 31 16 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POLY 15 0 rw Bits Fields Descriptions...

Page 138: ... CPU access to the system bus for some bus cycles Round robin scheduling is implemented in the bus matrix to ensure at least half of the system bus bandwidth for the CPU 8 2 Characteristics Programmable length of data to be transferred max to 65536 5 channels and each channel are configurable AHB and APB peripherals FLASH SRAM can be accessed as source and destination Each channel is connected to ...

Page 139: ...es for memory access and peripheral access An arbiter inside to manage multiple peripheral requests coming at the same time Channel management to control address data selection and data counting 8 4 Function overview 8 4 1 DMA operation Each DMA transfer consists of two operations including the loading of data from the source and the storage of the loaded data to the destination The source and des...

Page 140: ...e BC 7 0 0x3 16 bits 32 bits 1 Read B1B0 15 0 0x0 2 Read B3B2 15 0 0x2 3 Read B5B4 15 0 0x4 4 Read B7B6 15 0 0x6 1 Write 0000B1B0 31 0 0x0 2 Write 0000B3B2 31 0 0x4 3 Write 0000B5B4 31 0 0x8 4 Write 0000B7B6 31 0 0xC 16 bits 16 bits 1 Read B1B0 15 0 0x0 2 Read B3B2 15 0 0x2 3 Read B5B4 15 0 0x4 4 Read B7B6 15 0 0x6 1 Write B1B0 15 0 0x0 2 Write B3B2 15 0 0x2 3 Write B5B4 15 0 0x4 4 Write B7B6 15 0...

Page 141: ... a well organized and efficient data transfer a handshake mechanism is introduced between the DMA and peripherals including a request signal and a acknowledge signal Request signal asserted by peripheral to DMA controller indicating that the peripheral is ready to transmit or receive data Acknowledge signal responded by DMA to peripheral indicating that the DMA controller has initiated an AHB comm...

Page 142: ...ory In the fixed mode the next address is always equal to the base address configured in the base address registers DMA_CHxPADDR DMA_CHxMADDR In the increasing mode the next address is equal to the current address plus 1 or 2 or 4 depending on the transfer data width 8 4 5 Circular mode Circular mode is implemented to handle continue peripheral requests for example ADC scan mode The circular mode ...

Page 143: ...nfigure the DMA_CHxPADDR register for setting the peripheral base address 8 Configure the DMA_CHxMADDR register for setting the memory base address 9 Configure the DMA_CHxCNT register to set the total transfer data number 10 Configure the CHEN bit with 1 in the DMA_CHxCTL register to enable the channel 8 4 8 Interrupt Each DMA channel has a dedicated interrupt There are three types of interrupt ev...

Page 144: ...o one DMA channel They are logically ORed before entering the DMA For details see the Figure 8 4 DMA request mapping The request of each peripheral can be independently enabled or disabled by programming the registers of the corresponding peripheral The user has to ensure that only one request is enabled at a time on one channel Table 8 3 DMA requests for each channel lists the support request fro...

Page 145: ...R0_COM TIMER2_CH0 TIMER2_TRIG TIMER15_CH0 2 TIMER15_UP 2 or or Channel 3 M2M SPI1_TX USART0_RX 2 USART1_RX I2C1_RX TIMER0_CH2 TIMER0_UP TIMER14_CH0 TIMER14_UP TIMER14_TRIG TIMER14_COM TIMER14_CH1 or or Channel 4 M2M Table 8 3 DMA requests for each channel Peripheral Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 ADC ADC 1 ADC 2 SPI I2S SPI I2S0_RX SPI I2S0_TX SPI1_RX SPI1_TX USART USART0_TX 1 U...

Page 146: ...H0 1 TIMER15_UP 1 TIMER15_CH0 2 TIMER15_UP 2 TIMER16 TIMER16_CH0 1 TIMER16_UP 1 TIMER16_CH0 2 TIMER16_UP 2 1 When the corresponding remapping bit in the SYSCFG_CFG0 register is cleared the request is mapped on the channel 2 When the corresponding remapping bit in the SYSCFG_CFG0 register is set the request is mapped on the channel ...

Page 147: ... Transfer error has not occurred on channel x 1 Transfer error has occurred on channel x 18 14 10 6 2 HTFIFx Half transfer finish flag of channel x x 0 4 Hardware set and software cleared by configuring DMA_INTC register 0 Half number of transfer has not finished on channel x 1 Half number of transfer has finished on channel x 17 13 9 5 1 FTFIFx Full Transfer finish flag of channel x x 0 4 Hardwar...

Page 148: ...o effect 1 Clear half transfer finish flag 17 13 9 5 1 FTFIFCx Clear bit for full transfer finish flag of channel x x 0 4 0 No effect 1 Clear full transfer finish flag 16 12 8 4 0 GIFCx Clear global interrupt flag of channel x x 0 4 0 No effect 1 Clear GIFx ERRIFx HTFIFx and FTFIFx bits in the DMA_INTF register 8 5 3 Channel x control register DMA_CHxCTL x 0 4 where x is a channel number Address o...

Page 149: ...N is 1 9 8 PWIDTH 1 0 Transfer data size of peripheral Software set and cleared 00 8 bit 01 16 bit 10 32 bit 11 Reserved These bits can not be written when CHEN is 1 7 MNAGA Next address generation algorithm of memory Software set and cleared 0 Fixed address mode 1 Increasing address mode This bit can not be written when CHEN is 1 6 PNAGA Next address generation algorithm of peripheral Software se...

Page 150: ...ull transfer finish interrupt Software set and cleared 0 Disable channel full transfer finish interrupt 1 Enable channel full transfer finish interrupt 0 CHEN Channel enable Software set and cleared 0 Disable channel 1 Enable channel 8 5 4 Channel x counter register DMA_CHxCNT x 0 4 where x is a channel number Address offset 0x0C 0x14 x Reset value 0x0000 0000 This register has to be accessed by w...

Page 151: ...31 16 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PADDR 15 0 rw Bits Fields Descriptions 31 0 PADDR 31 0 Peripheral base address These bits can not be written when CHEN in the DMA_CHxCTL register is 1 When PWIDTH is 01 16 bit the LSB of these bits is ignored Access is automatically aligned to a half word address When PWIDTH is 10 32 bit the two LSBs of these bits are ignored Access is automatically a...

Page 152: ...ter is 1 When MWIDTH in the DMA_CHxCTL register is 01 16 bit the LSB of these bits is ignored Access is automatically aligned to a half word address When MWIDTH in the DMA_CHxCTL register is 10 32 bit the two LSBs of these bits are ignored Access is automatically aligned to a word address ...

Page 153: ...onding bit is set it provides a clock in power saving mode or holds the state for TIMER I2C RTC WWDGT and FWDGT 9 2 SW function overview Debug capabilities can be accessed by a debug tool via Serial Wire SW Debug Port 9 2 1 Pin assignment The synchronous serial wire debug SWD provide 2 pin SW interface known as SW data input output SWDIO and SW clock SWCLK The pin assignment is as following PA14 S...

Page 154: ...ep mode the clock of AHB bus for CPU is not closed and the debugger can debug in sleep mode 9 3 2 Debug support for TIMER I2C RTC WWDGT and FWDGT When the core is halted and the corresponding bit in DBG control register 0 or DBG control register 1 DBG_CTL0 or DBG_CTL1 is set the following events occur For TIMER the timer counters are stopped and held for debugging For I2C SMBUS timeout is held for...

Page 155: ... 0x04 Reset value 0x0000 0000 power reset only This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved TIMER13_ HOLD Reserved TIMER5_ HOLD Reserved I2C1_HOL D rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I2C0_HOL D Reserved TIMER2_ HOLD Reserved TIMER0_ HOLD WWDGT_ HOLD FWDGT_ HOLD Reserved STB_ HOLD DSLP_ HOLD SLP_ HOLD rw rw rw rw rw rw rw rw Bi...

Page 156: ...MER 2 counter for debugging when the core is halted 11 Reserved Must be kept at reset value 10 TIMER0_HOLD TIMER 0 hold bit This bit is set and reset by software 0 no effect 1 hold the TIMER 0 counter for debugging when the core is halted 9 WWDGT_HOLD WWDGT hold bit This bit is set and reset by software 0 no effect 1 hold the WWDGT counter clock for debugging when the core is halted 8 FWDGT_HOLD F...

Page 157: ...1 10 9 8 7 6 5 4 3 2 1 0 Reserved RTC_HO LD Reserved rw Bits Fields Descriptions 31 19 Reserved Must be kept at reset value 18 TIMER16_HOLD TIMER 16 hold bit This bit is set and reset by software 0 no effect 1 hold the TIMER 16 counter for debugging when the core is halted 17 TIMER15_HOLD TIMER 15 hold bit This bit is set and reset by software 0 no effect 1 hold the TIMER 15 counter for debugging ...

Page 158: ...GD32E23x User Manual 158 9 0 Reserved Must be kept at reset value ...

Page 159: ...tion function Programmable sampling time Data storage mode the most significant bit and the least significant bit DMA support Dual clock domain architecture APB clock and ADC clock Analog input channels 10 external analog inputs 1 channel for internal temperature sensor VSENSE 1 channel for internal reference voltage VREFINT Start of conversion can be initiated By software By hardware triggers Ope...

Page 160: ...DC input pins definition give the ADC internal signals and pins description Table 10 1 ADC internal input signals Internal signal name Description VSENSE Internal temperature sensor output voltage VREFINT Internal voltage reference output voltage Table 10 2 ADC input pins definition Name Description VDDA Analog power supply equals to VDD and 2 4V VDDA 3 6 V VSSA Ground for analog power supply equa...

Page 161: ... ADC calculates a calibration factor which is internally applied to the ADC until the next ADC power off The application can not use the ADC until the calibration is completed The calibration should be performed before starting A D conversion The calibration is initiated by setting the CLB bit to 1 The CLB bit stays at 1 during the calibration sequence It is then cleared by hardware as soon as the...

Page 162: ...equence The channel management circuit can organize the sampling conversion channels into a sequence routine sequence The routine sequence supports up to 16 channels and each channel is called routine channel The RL 3 0 bits in the ADC_RSQ0 register specify the total conversion sequence length The ADC_RSQ0 ADC_RSQ2 registers specify the selected channels of the routine sequence operation modes 10 ...

Page 163: ...rsion data will be stored in the ADC_RDATA register Figure 10 3 Continuous operation mode CH2 CH2 CH2 CH2 CH2 CH2 EOC Routine trigger Sample Convert CH2 Software procedure for continuous operation mode on a routine channel 1 Set the CTN bit in the ADC_CTL1 register 2 Configure the RSQ0 with the analog channel number 3 Configure the ADC_SAMPTx register 4 Configure the ETERC and ETSRC bits in the AD...

Page 164: ...de continuous disable CH2 CH1 CH5 CH7 CH11 CH16 CH2 CH1 EOC One circle of routine sequence RL 7 Routine trigger CH12 CH17 Software procedure for scan operation mode on a routine sequence 1 Set the SM bit in the ADC_CTL0 register and the DMA bit in the ADC_CTL1 register 2 Configure the ADC_RSQx and ADC_SAMPTx registers 3 Configure the ETERC and ETSRC bits in the ADC_CTL1 register if it is needed 4 ...

Page 165: ...he SWRCST bit or generate an external trigger for the routine sequence 7 Repeat step6 if in need 8 Wait the EOC flag to be set 9 Clear the EOC flag by writing 0 to it 10 4 6 Conversion result threshold monitor function The analog watchdog is enabled when the RWDEN bit in the ADC_CTL0 register is set for routine sequence This function is used to monitor whether the conversion result exceeds the set...

Page 166: ...AL 1 Routine channel data Figure 10 8 Data storage mode of 10 bit resolution 0 0 0 0 0 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Routine channel data 0 0 0 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 DAL 0 DAL 1 Routine channel data Figure 10 9 Data storage mode of 8 bit resolution 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 Routine channel data 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 DAL 0 DAL 1 Routine channel data F...

Page 167: ... Hardware trigger 001 TIMER0_CH1 010 TIMER0_CH2 011 reserved 100 TIMER2_TRGO 101 TIMER14_CH0 110 EXTI_11 111 SWRCST Software trigger 10 4 10 DMA request The DMA request which is enabled by the DMA bit in ADC_CTL1 register is used to transfer data of routine sequence for conversion of more than one channel The ADC generates a DMA request at the end of conversion of a routine channel When this reque...

Page 168: ...ature C V25 Vtemperature Avg_Slope 25 V25 internal temperature sensor output voltage at 25 C the typical value please refer to the datasheet Avg_Slope average slope for curve between Temperature vs internal temperature sensor output voltage the typical value please refer to the datasheet 10 4 12 Programmable resolution DRES fast conversion mode It is possible to obtain faster conversion time tADC ...

Page 169: ... means bit right shifting up to 8 bits It is configured through the OVSS 3 0 bits in the ADC_OVSAMPCTL register Summation units can produce up to 20 bits 256 x 12 bit which is first shifted right The upper bits of the result are then truncated keeping only the 16 least significant bits rounded to the nearest value using the least significant bits left apart by the shifting before being finally tra...

Page 170: ...x07FF 0x03FF 0x01FF 0x00FF 0x007F 0x003F 8x 0x7FF8 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x07FF 0x03FF 0x01FF 0x00FF 0x007F 16x 0xFFF0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x07FF 0x03FF 0x01FF 0x00FF 32x 0x1FFE0 0xFFE0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x07FF 0x03FF 0x01FF 64x 0x3FFC0 0xFFC0 0xFFE0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x07FF 0x03FF 128x 0x7FF80 0xFF80 0xFFC0 0xFFE0 0xFFF0 0x7FF8 0x3FFC 0x1FFE ...

Page 171: ...n ADCON is reset Make sure configuring the oversampling before setting ADCON to 1 10 4 14 ADC interrupts The interrupt can be produced on one of the events End of conversion for routine sequence The analog watchdog event Separate interrupt enable bits are available for flexibility ...

Page 172: ... started Set by hardware when routine sequence conversion starts Cleared by software writing 0 to it 3 2 Reserved Must be kept at reset value 1 EOC End flag of routine sequence conversion 0 No end of routine sequence conversion 1 End of routine sequence conversion Set by hardware at the end of a routine sequence conversion Cleared by software writing 0 to it or by reading the ADC_RDATA register 0 ...

Page 173: ...e kept at reset value 15 13 DISNUM 2 0 Number of conversions in discontinuous mode The number of channels to be converted after a trigger will be DISNUM 2 0 1 12 Reserved Must be kept at reset value 11 DISRC Discontinuous mode on routine sequence 0 Discontinuous operation mode disable 1 Discontinuous operation mode enable 10 Reserved Must be kept at reset value 9 WDSC When in scan mode analog watc...

Page 174: ...rved ETERC ETSRC 2 0 Reserved rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DAL Reserved DMA Reserved RSTCLB CLB CTN ADCON rw rw rw rw rw rw Bits Fields Descriptions 31 24 Reserved Must be kept at reset value 23 TSVREN Channel 16 and 17 enable of ADC 0 Channel 16 and 17 of ADC disable 1 Channel 16 and 17 of ADC enable 22 SWRCST Software start on conversion of routine sequence Set 1 on...

Page 175: ... calibration registers are initialized 0 Calibration register initialization done 1 Calibration register initialization starts 2 CLB ADC calibration 0 Calibration done 1 Calibration start 1 CTN Continuous mode 0 Continuous operation mode disable 1 Continuous operation mode enable 0 ADCON ADC ON The ADC will be waked up when this bit is changed from low to high and take a stabilization time When th...

Page 176: ... is 55 5 cycles 110 channel sampling time is 71 5 cycles 111 channel sampling time is 239 5 cycles 17 0 Reserved Must be kept at reset value 10 5 5 Sample time register 1 ADC_SAMPT1 Address offset 0x10 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved SPT9 2 0 SPT8 2 0 SPT7 2 0 SPT6 2 0 SPT5 2 1 rw rw rw rw rw 15 14 13 ...

Page 177: ...110 channel sampling time is 71 5 cycles 111 channel sampling time is 239 5 cycles 10 5 6 Watchdog low threshold register ADC_WDLT Address offset 0x28 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WDLT 11 0 rw Bits Fields Descriptions 31 12 Reserved Must be kept at rese...

Page 178: ... description 10 5 8 Routine sequence register 1 ADC_RSQ1 Address offset 0x30 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved RSQ11 4 0 RSQ10 4 0 RSQ9 4 1 rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSQ9 0 RSQ8 4 0 RSQ7 4 0 RSQ6 4 0 rw rw rw rw Bits Fields Descriptions 31 30 Reserved Must be kept at reset value 29 2...

Page 179: ...on 19 15 RSQ3 4 0 Refer to RSQ0 4 0 description 14 10 RSQ2 4 0 Refer to RSQ0 4 0 description 9 5 RSQ1 4 0 Refer to RSQ0 4 0 description 4 0 RSQ0 4 0 The channel number 0 9 16 17 is written to these bits to select a channel as the nth conversion in the routine sequence 10 5 10 Routine data register ADC_RDATA Address offset 0x4C Reset value 0x0000 0000 This register has to be accessed by word 32 bit...

Page 180: ...rigger 1 Each conversion needs a trigger for a oversampled channel and the number of triggers is determined by the oversampling ratio OVSR 2 0 Note The software allows this bit to be written only when ADCON 0 this ensures that no conversion is in progress 8 5 OVSS 3 0 Oversampling shift These bits are set and cleared by software 0000 No shift 0001 Shift 1 bit 0010 Shift 2 bits 0011 Shift 3 bits 01...

Page 181: ... 0 this ensures that no conversion is in progress 1 Reserved Must be kept at reset value 0 OVSEN Oversampling enable This bit is set and cleared by software 0 Oversampling disabled 1 Oversampling enabled Note The software allows this bit to be written only when ADCON 0 this ensures that no conversion is in progress ...

Page 182: ...r with the timers 11 2 Main features Rail to rail comparators Configurable hysteresis Configurable speed and consumption Configurable analog input source CMP input pins The whole or sub multiple values of internal reference voltage Outputs to I O Outputs to timers for triggering Outputs to EXTI 11 3 Function description The block diagrams of CMP are shown as below ...

Page 183: ...CMP output to the TIMER break CMP output to the TIMER OCPRE_CLR In order to work even in deep sleep mode the polarity selection logic and the output redirection to the port work independently from PCLK The CMP output can be redirected internally and externally simultaneously Each CMP has its own EXTI line and it could generate either interrupts or events whitchmake the CMP exit from power saving m...

Page 184: ...y using external components This function could be shut down if it is unnecessary Figure 11 2 CMP hysteresis CMP_IM Vhyst CMP_OUT CMP_IM Vhyst CMP_IM CMP_IP 11 3 5 CMP register write protection The CMP control and status register CMP_CS could be protected from writing by setting CMPLK bit to 1 The CMP_CS register including the CMPLK bit will be read only and can only be reset by the MCU reset ...

Page 185: ...y It can only be set once by software and cleared by a system reset 0 CMP_CS 15 0 bits are read write 1 CMP_CS 15 0 bits are read only 14 CMPO CMP output This bit is a copy of CMP output state which is read only 0 Non inverting input below inverting input and the output is low 1 Non inverting input above inverting input and the output is high 13 12 CMPHST 1 0 CMP hysteresis These bits are used to ...

Page 186: ...ource connected to the CMP_IM input of the CMP 000 VREFINT 4 001 VREFINT 2 010 VREFINT 3 4 011 VREFINT 100 PA4 101 PA5 110 PA0 111 PA2 3 2 CMPM 1 0 CMP mode These bits are used to control the operating mode of the CMP 00 High speed full power 01 Medium speed medium power 10 Low speed low power 11 Very low speed ultra low power 1 CMPSW CMP switch This bit is used to closes a switch between CMP non ...

Page 187: ...nt environment and lower timing accuracy The free watchdog timer causes a reset when the internal down counter reaches 0 or the counter is refreshed when the value of the counter is greater than the window register value The register write protection function in free watchdog can be enabled to prevent it from changing the configuration unexpectedly 12 1 2 Characteristics Free running 12 bit down c...

Page 188: ... value of the FWDGT_WND is 0x0000 0FFF so if it is not updated the window option is disabled A reload operation is performed in order to reset the downcounter to the FWDGT_RLD value and the prescaler counter to generate the next reload as soon as the window value is changed The free watchdog can automatically start at power on when the hardware free watchdog bit in the device option bits is set To...

Page 189: ...38 025 1 32 011 0 025 3276 025 1 64 100 0 025 6552 025 1 128 101 0 025 13104 025 1 256 110 or 111 0 025 26208 025 The FWDGT timeout can be more accurately by calibrating the IRC40K Note When after the execution of watchdog reload operation if the MCU needs enter the deepsleep standby mode immediately more than 3 IRC40K clock intervals must be inserted in the middle of reload and deepsleep standby ...

Page 190: ...alues 0x5555 Disable the FWDGT_PSC FWDGT_RLD and FWDGT_WND write protection 0xCCCC Start the free watchdog timer counter When the counter reduces to 0 the free watchdog generates a reset 0xAAAA Reload the counter Prescaler register FWDGT_PSC Address offset 0x04 Reset value 0x0000 0000 This register can be accessed by half word 16 bit or word 32 bit access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 ...

Page 191: ...8 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved RLD 11 0 rw Bits Fields Descriptions 31 12 Reserved Must be kept at reset value 11 0 RLD 11 0 Free watchdog timer counter reload value Write 0xAAAA in the FWDGT_CTL register will reload the FWDGT conter with the RLD value These bits are write protected Write 0X5555 to the FWDGT_CTL register before writing...

Page 192: ...ster this bit is set and the value read from FWDGT_RLD register is invalid 0 PUD Free watchdog timer prescaler value update During a write operation to FWDGT_PSC register this bit is set and the value read from FWDGT_PSC register is invalid Window register FWDGT_WND Address offset 0x10 Reset value 0x0000 0FFF This register can be accessed by half word 16 bit or word 32 bit access 31 30 29 28 27 26...

Page 193: ...ister before writing these bits If several window values are used by the application it is mandatory to wait until WUD bit has been reset before changing the window value However after updating the window value it is not necessary to wait until WUD is reset before continuing code execution except in case of low power mode entry Before entering low power mode it is necessary to wait until PUD is re...

Page 194: ...dow watchdog timer clock is prescaled from the APB1 clock The window watchdog timer is suitable for the situation that requires an accurate timing 12 2 2 Characteristics Programmable free running 7 bit down counter Generate reset in two conditions when WWDGT is enabled Reset when the counter reached 0x3F The counter is refreshed when the value of the counter is greater than the window register val...

Page 195: ...ter WWDGT_CFG specifies the window value The software can prevent the reset event by reloading the down counter The counter value is less than the window value and greater than 0x3F otherwise the watchdog causes a reset The early wakeup interrupt EWI is enabled by setting the EWIE bit in the WWDGT_CFG register and the interrupt will be generated when the counter reaches 0x40 or the counter is refr...

Page 196: ... APB1 clock period measured in ms The table below shows the minimum and maximum values of the tWWDGT Table 12 2 Min max timeout value at 72 MHz fPCLK1 Prescaler divider PSC 1 0 Min timeout value CNT 6 0 0x40 Max timeout value CNT 6 0 0x7F 1 1 00 56 μs 3 64 ms 1 2 01 113 μs 7 28 ms 1 4 10 227 μs 14 56 ms 1 8 11 455 μs 29 12 ms If the WWDGT_HOLD bit in DBG module is cleared the WWDGT continues to wo...

Page 197: ...chdog timer disabled 1 Window watchdog timer enabled 6 0 CNT 6 0 The value of the watchdog timer counter A reset occur when the value of this counter decreases from 0x40 to 0x3F When the value of this counter is greater than the window value writing this counter also causes a reset Configuration register WWDGT_CFG Address offset 0x04 Reset value 0x0000 007F This register can be accessed by half wo...

Page 198: ... counter is greater than the Window value Status register WWDGT_STAT Address offset 0x08 Reset value 0x0000 0000 This register can be accessed by half word 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved EWIF rw Bits Fields Descriptions 31 1 Reserved Must be kept at reset value 0 EWIF Early wakeup interrupt flag When the...

Page 199: ...tware External high accurate low frequency 50Hz or 60Hz clock used to achieve higher calendar accuracy performed by reference clock detection option function Atomic clock adjustment max adjustment accuracy is 0 95PPM for calendar calibration performed by digital calibration function Sub second adjustment by shift function Time stamp function for saving event time Two Tamper sources can be chosen a...

Page 200: ...Hz ck_spre Default 1 Hz 512Hz 1Hz Alarm 0 Flag RTC_CALIB ALARM 0 Output Selection Logic RTC_OUT RTC Block Diagram RTC_TAMP0 RTC_TAMP1 RTC_ALARM Alarm 0 logic The RTC unit includes Alarm event interrupt Tamper event interrupt 32 bit backup registers Optional RTC output function GD32E231xx devices do not have this function 512Hz default prescale RTC_OUT 1Hz default prescale RTC_OUT Alarm event polar...

Page 201: ...AD control bit decides the location when APB bus accesses the RTC calendar register RTC_DATE RTC_TIME and RTC_SS By default the BPSHAD is cleared and APB bus accesses the shadow calendar registers Shadow calendar registers is updated with the value of real calendar registers every two RTC clock and at the same time RSYNF bit will be set once This update mechanism is not performed in Deep Sleep mod...

Page 202: ...others are not RTC_TIME RTC_DATE RTC_CTL RTC_STAT RTC_PSC RTC_ALRMxTD RTC_SHIFTCTL RTC_HRFC RTC_ALRMxSS Calendar initialization and configuration The prescaler and calendar value can be programmed by the following steps 1 Enter initialization mode by setting INITM 1 and polling INITF bit until INITF 1 2 Program both the asynchronous and synchronous prescaler factors in RTC_PSC register 3 Write the...

Page 203: ... case When APB1 bus clock frequency is not equal to or greater than 7 times the RTC clock frequency the calendar reading flow should be obeyed 1 reading calendar time register and date register twice 2 if the two values are equal the value can be seen as the correct value 3 if the two values are not equal a third reading should performed 4 the third value can be seen as the correct value RSYNF is ...

Page 204: ...alue of the calendar register read out might be not correct To ensure the correctness and consistency of the calendar value software must perform reading operation as this read all calendar registers continuously if the last two values are the same the data is coherent and correct 13 3 7 Resetting the RTC There are two reset sources used in RTC unit system reset and backup domain reset System rese...

Page 205: ...g RTC_SHIFTCTL register the SOPF bit in RTC_STAT will be set at once When shift operation is complete SOPF bit is cleared by hardware System reset does not affect SOPF bit Shift operation only works correctly when REFEN 0 Software must not write to RTC_SHIFTCTL if REFEN 1 13 3 9 RTC reference clock detection RTC reference clock detection is another way to increase the precision of RTC second To en...

Page 206: ...on is equally executed in a period time and the cycle number of the RTC clock in the period time will be added or subtracted The resolution of the calibration is about 0 954PPM with the range from 487 1PPM to 488 5PPM The calibration period time can be configured to the 220 219 218 RTC clock cycles which stands for 32 16 8 seconds if RTC input frequency is 32 768 KHz The High resolution frequency ...

Page 207: ... the RTC precision Up to 2 RTC clock cycles measurement error may occur when measuring the RTC frequency over a limited measurement period To eliminate this measurement error the measurement period should be the same as the calibration period When the calibration period is 32 seconds this is default configuration Using exactly 32s period to measure the accuracy of the calibration 1Hz output can gu...

Page 208: ...2 Tamper detection The RTC_TAMPx pin input can be used for tamper event detection under edge detection mode or level detection mode with configurable filtering setting RTC backup registers RTC_BKPx The RTC backup registers are located in the VDD backup domain The wake up action from Standby Mode or System Reset does not affect these registers These registers are only reset by detected tamper event...

Page 209: ...8 needed for valid level When DISPU is set to 0x0 this is default the internal pull up resistance will pre charge the tamper input pin before each sampling and thus larger capacitance is allowed to connect to the tamper input pin The pre charge duration is configured through PRCH bit Higher capacitance needs long pre charge time The time interval between each sampling is also configurable Through ...

Page 210: ... in Mode Exit Mode Sleep Yes RTC Interrupts Deep Sleep Yes if clock source is LXTAL or IRC40K RTC Alarm Tamper Event Standby Yes if clock source is LXTAL or IRC40K RTC Alarm Tamper Event 13 3 16 RTC interrupts All RTC interrupts are connected to the EXTI controller Below steps should be followed if you want to use the RTC alarm tamper timestamp 1 Configure and enable the corresponding interrupt li...

Page 211: ...ly active when RTC clock source is LXTAL or IRC40K For GD32E231xx devices Interrupt Event flag Control Bit Exit Sleep Exit Deep sleep Exit Standby Alarm 0 ALRM0F ALRM0IE Y Y Y Tamper 1 TP1F TPIE Y Y Y Only active when RTC clock source is LXTAL or IRC40K ...

Page 212: ... 2 0 MNU 3 0 Reserved SCT 2 0 SCU 3 0 rw rw rw rw Bits Fields Descriptions 31 23 Reserved Must be kept at reset value 22 PM AM PM mark 0 AM or 24 hour format 1 PM 21 20 HRT 1 0 Hour tens in BCD code 19 16 HRU 3 0 Hour units in BCD code 15 Reserved Must be kept at reset value 14 12 MNT 2 0 Minute tens in BCD code 11 8 MNU 3 0 Minute units in BCD code 7 Reserved Must be kept at reset value 6 4 SCT 2...

Page 213: ...Month tens in BCD code 11 8 MONU 3 0 Month units in BCD code 7 6 Reserved Must be kept at reset value 5 4 DAYT 1 0 Day tens in BCD code 3 0 DAYU 3 0 Day units in BCD code 13 4 3 Control register RTC_CTL For GD32E230xx devices Address offset 0x08 System reset not affected Backup domain reset value 0x0000 0000 This register is writing protected This register has to be accessed by word 32 bit 31 30 2...

Page 214: ...t is 512 Hz 1 Calibration output is 1Hz 18 DSM Daylight saving mark This bit is flexible used by software Often can be used to recording the daylight saving hour adjustment 17 S1H Subtract 1 hour winter time change One hour will be subtracted from current time if it is not 0 0 No effect 1 1 hour will be subtracted at next second change time 16 A1H Add 1 hour summer time change One hour will be add...

Page 215: ... Disable reference clock detection function 1 Enable reference clock detection function Note Can only be written in initialization state and FACTOR_S must be 0x00FF 3 TSEG Valid event edge of time stamp 0 rising edge is valid event edge for time stamp event 1 falling edge is valid event edge for time stamp event 2 0 Reserved Must be kept at reset value For GD32E231xx devices Address offset 0x08 Sy...

Page 216: ...Alarm 0 function enable 0 Disable alarm function 1 Enable alarm function 7 Reserved Must be kept at reset value 6 CS Clock System 0 24 hour format 1 12 hour format Note Can only be written in initialization state 5 BPSHAD Shadow registers bypass control 0 Reading calendar from shadow registers 1 Reading calendar from current real time calendar Note If frequency of APB1 clock is less than seven tim...

Page 217: ... to RTC_HRFC without entering initialization mode and set to 0 by hardware when smooth calibration configuration is taken into account 15 Reserved Must be kept at reset value 14 TP1F RTC_TAMP1 detected flag Set to 1 by hardware when tamper detection is found on tamper1 input pin Software can clear this bit by writing 0 into this bit 13 TP0F RTC_TAMP0 detected flag Set to 1 by hardware when tamper ...

Page 218: ...dow register are not yet synchronized 1 Shadow register are synchronized 4 YCM Year configuration mark Set by hardware if the year field of calendar date register is not the default value 0 0 Calendar has not been initialized 1 Calendar has been initialized 3 SOPF Shift function operation pending flag 0 No shift operation is pending 1 Shift function operation is pending 2 1 Reserved Must be kept a...

Page 219: ...etting value Cleared by software writing 0 7 INITM Enter initialization mode 0 Free running mode 1 Enter initialization mode for setting calendar time date and prescaler Counter will stop under this mode 6 INITF Initialization state flag Set to 1 by hardware calendar registers and prescaler can be programmed in this state 0 Calendar registers and prescaler register cannot be changed 1 Calendar reg...

Page 220: ...accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved FACTOR_A 6 0 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FACTOR_S 14 0 rw Bits Fields Descriptions 31 23 Reserved Must be kept at reset value 22 16 FACTOR_A 6 0 Asynchronous prescaler factor ck_apre frequency RTCCLK frequency FACTOR_A 1 15 Reserved Must be kept at reset value 14 0 FACTOR_S 14 0 Synchronous presc...

Page 221: ... DAYU 3 0 Date units or week day in BCD code 23 MSKH Alarm hour mask bit 0 Not mask hour field 1 Mask hour field 22 PM AM PM flag 0 AM or 24 hour format 1 PM 21 20 HRT 1 0 Hour tens in BCD code 19 16 HRU 3 0 Hour units in BCD code 15 MSKM Alarm minutes mask bit 0 Not mask minutes field 1 Mask minutes field 14 12 MNT 2 0 Minutes tens in BCD code 11 8 MNU 3 0 Minutes units in BCD code 7 MSKS Alarm s...

Page 222: ... 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SSC 15 0 r Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 SSC 15 0 Sub second value This value is the counter value of synchronous prescaler Second fraction value is calculated by the below formula Second fraction FACTOR_S SSC FACTOR_S 1 13 4 9 Shift function control register R...

Page 223: ... and SFS the clock will advance Advance seconds 1 SFS FACTOR_S 1 Note Writing to this register will cause RSYNF bit to be cleared 13 4 10 Time of time stamp register RTC_TTS Address offset 0x30 Backup domain reset value 0x0000 0000 System reset no effect This register will record the calendar time when TSF is set to 1 Reset TSF bit will also clear this register This register has to be accessed by ...

Page 224: ... has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DOW 2 0 MONT MONU 3 0 Reserved DAYT 1 0 DAYU 3 0 r r r r r Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 13 DOW 2 0 Days of the week 12 MONT Month tens in BCD code 11 8 MONU 3 0 Month units in BCD code 7 6 Reserved Must be kept at reset value 5 ...

Page 225: ...ed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FREQI CWND8 CWND16 Reserved CMSK 8 0 rw rw rw rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 FREQI Increase RTC frequency by 488 5PPM 0 No effect 1 One RTCCLK pulse is inserted every 211 pulses This bit should be used in conjunction with CMSK bit If the input ...

Page 226: ...rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DISPU PRCH 1 0 FLT 1 0 FREQ 2 0 TPTS Reserved TP1EG TP1EN TPIE TP0EG TP0EN rw rw rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 24 Reserved Must be kept at reset value 23 PC15MDE PC15 Mode 0 No effect 1 Force PC15 to push pull output if LXTAL is disable 22 PC15VAL PC15 Value Only valid when LXTAL is disabled and PC15MDE 1 PC15 output this bit ...

Page 227: ...secutive valid level samples will make an effective tamper event 0x2 Detecting tamper event using level mode 4 consecutive valid level samples will make an effective tamper event 0x3 Detecting tamper event using level mode 8 consecutive valid level samples will make an effective tamper event 10 8 FREQ 2 0 Sampling frequency of tamper event detection 0x0 Sample once every 32768 RTCCLK 1Hz if RTCCLK...

Page 228: ...s a tamper detection event If tamper detection is in level mode FLT 0 0 Low level triggers a tamper detection event 1 High level triggers a tamper detection event 0 TP0EN Tamper 0 detection enable 0 Disable tamper 0 detection function 1 Enable tamper 0 detection function Note It s strongly recommended that reset the TPxEN before change the tamper configuration For GD32E231xx devices Address offset...

Page 229: ...secutive sample 0x0 Detecting tamper event using edge mode Pre charge duration is disabled automatically 0x1 Detecting tamper event using level mode 2 consecutive valid level samples will make an effective tamper event 0x2 Detecting tamper event using level mode 4 consecutive valid level samples will make an effective tamper event 0x3 Detecting tamper event using level mode 8 consecutive valid lev...

Page 230: ...lue Note It s strongly recommended that reset the TPxEN before change the tamper configuration 13 4 15 Alarm 0 sub second register RTC_ALRM0SS Address offset 0x44 Backup domain reset 0x0000 0000 System reset no effect This register is write protected and can only be wrote when ALRM0EN 0 or INITM 1 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reser...

Page 231: ...and all others are ignored Note The bit 15 of synchronous counter SSC 15 in RTC_SS is never compared 23 15 Reserved Must be kept at reset value 14 0 SSC 14 0 Alarm sub second value This value is the alarm sub second value which is to be compared with synchronous prescaler counter SSC Bit number is controlled by MSKSSC bits 13 4 16 Backup registers RTC_BKPx x 0 4 Address offset 0x50 0x60 Backup dom...

Page 232: ...ode UP DOWN Center aligne d UP DOWN Center align ed UP ONLY UP ONLY UP ONLY UP ONLY Repetition CH Capture Compare 4 4 1 2 1 0 Complementary Dead time Break Single Pulse Quadrature Decoder Master slave management Inter connection 1 2 3 DMA 4 Debug Mode 1 TIMER0 ITI0 TIMER14_TRGO ITI1 0 ITI2 TIMER2_TRGO ITI3 0 2 TIMER2 ITI0 TIMER0_TRGO ITI1 0 ITI2 TIMER14_TRGO ITI3 0 3 TIMER14 ITI0 0 ITI1 TIMER2_TRG...

Page 233: ...nnel num 4 Counter width 16 bits Clock source of timer is selectable internal clock internal trigger external input external trigger Multiple counter modes up counting down counting and center aligned counting Quadrature decoder used for motion tracking and determination of both rotation direction and position Hall sensor function used for 3 phase motor control Programmable prescaler 16 bits The f...

Page 234: ...r Interrupt Register set and update Interrupt collector and controller APB BUS CK_TIMER CH0_IN CH1_IN CH2_IN CH3_IN CI0 ITI0 ITI1 ITI2 ITI3 ETI CAR Repeater Output Logic generation of outputs signals in compare PWM and mixed modes according to initialization complementary mode software output control deadtime insertion break input output mask and polarity control BRKEN BRKI N CKM clock monitor CH0...

Page 235: ...s clocked by other clock sources selected by the TRGS 2 0 in the TIMERx_SMCFG register details as follows When the SMC 2 0 bits are set to 0x4 0x5 or 0x6 the internal clock CK_TIMER is the counter prescaler driving clock source Figure 14 2 Timing chart of internal clock divided by 1 CK_TIMER CEN PSC_CLK TIMER_CK CNT_REG Reload Pulse 17 18 19 20 21 22 update event generate UPG 23 00 01 02 03 04 05 ...

Page 236: ...ircuitry will generate a clock pulse on each ETI signal rising edge to clock the counter prescaler Clock prescaler The counter clock PSC_CK is obtained by the TIMER_CK through the prescaler and the prescale factor can be configured from 1 to 65536 through the prescaler register TIMERx_PSC The new written prescaler value will not take effect until the next update event Figure 14 3 Timing chart of P...

Page 237: ...ate event is disabled When an update event occurs all the shadow registers repetition counter counter auto reload register prescaler register are updated Figure 14 4 Timing chart of up counting mode PSC 0 2 and Figure 14 5 Timing chart of up counting mode change TIMERx_CAR on the go show some examples of the counter behavior for different clock prescaler factor when TIMERx_CAR 0x99 Figure 14 4 Tim...

Page 238: ...ter the counter will start counting down from the counter reload value again and an underflow event will be generated In addition the update event will be generated after TIMERx_CREP 1 times of underflow The counting direction bit DIR in the TIMERx_CTL0 register should be set to 1 for the down counting mode When the update event is set by the UPG bit in the TIMERx_SWEVG register the counter value ...

Page 239: ...LK 2 1 0 99 98 Figure 14 7 Timing chart of down counting mode change TIMERx_CAR on the go TIMER_CK CEN PSC_CLK CNT_REG 5 4 3 2 1 0 99 98 97 96 95 94 93 92 Update event UPE Update interrupt flag UPIF Auto reload register 120 99 change CAR Vaule CNT_REG 5 4 3 2 1 0 99 1 0 120 Update event UPE Update interrupt flag UPIF Auto reload register 120 99 change CAR Vaule 120 99 Auto reload shadow register H...

Page 240: ...egister will initialize the counter value to 0 and generates an update event irrespective of whether the counter is counting up or down in the center align counting mode The UPIF bit in the TIMERx_INTF register can be set to 1 either when an underflow event or an overflow event occurs While the CHxIF bit is associated with the value of CAM in TIMERx_CTL0 The details refer to Figure 14 8 Timing cha...

Page 241: ...repetition is used to generator update event or updates the timer registers only after a given number N 1 of cycles of the counter where N is CREP in TIMERx_CREP register The repetition counter is decremented at each counter overflow does not exist in down counting mode and underflow does not exist in up counting mode Setting the UPG bit in the TIMERx_SWEVG register will reload the content of CREP...

Page 242: ...on the overflow Figure 14 9 Repetition counter timing chart of center aligned counting mode CEN 3 2 1 0 1 2 98 99 98 2 1 0 Underflow Overflow TIMERx_CREP 0x0 TIMER_CK 1 2 98 99 98 2 UPIF TIMERx_CREP 0x1 1 0 1 2 98 99 98 97 UPIF UPIF TIMERx_CREP 0x2 PSC_CLK Figure 14 10 Repetition counter timing chart of up counting mode CEN CNT_REG 96 97 98 99 0 1 98 99 0 1 98 99 Underflow Overflow TIMERx_CREP 0x0...

Page 243: ... is built around a channel capture compare register including an input stage a channel controller and an output stage Channel input capture function Channel input capture function allows the channel to perform measurements such as pulse timing frequency period duty cycle and so on The input stage consists of a digital filter a channel polarity selection edge detection and a channel prescaler When ...

Page 244: ... input capture signal can also be selected from the input signal of other channel or the internal trigger signal by configuring CHxMS bits The IC prescaler makes several input events generate one effective capture event On the capture event TIMERx_CHxCV will store the value of counter So the process can be divided into several steps as below Step1 Filter configuration CHxCAPFLT in TIMERx_CHCTL0 Ba...

Page 245: ...1CV can measure the PWM duty cycle Channel output compare function Figure 14 13 Channel output compare principle with complementary output x 0 1 2 Capture compare register CHxCV Counter output comparator Compare output control CHxCOMCTL CNT CHxCV CNT CHxCV CNT CHxCV Output complementary protection register Dead Time Output enable and polarity selector CHxP CHxNP CHxE CHxNE OxCPRE CHx_O CHx_ON Figu...

Page 246: ...pulses with programmable position polarity duration and frequency When the counter matches the value in the TIMERx_CHxCV register of an output compare channel the channel n output can be set cleared or toggled based on CHxCOMCTL When the counter reaches the value in the TIMERx_CHxCV register the CHxIF bit will be set and the channel n interrupt is generated if CHxIE 1 And the DMA request will be a...

Page 247: ...APWM Edge aligned PWM and CAPWM Center aligned PWM The EAPWM s period is determined by TIMERx_CAR and the duty cycle is determined by TIMERx_CHxCV Figure 14 16 Timing chart of EAPWM shows the EAPWM output and interrupts waveform The CAPWM s period is determined by 2 TIMERx_CAR and the duty cycle is determined by 2 TIMERx_CHxCV Figure 14 17 Timing chart of CAPWM shows the CAPWM output and interrupt...

Page 248: ...IF CAM 2 b11 up down CHxIF Channel output prepare signal As is shown in Figure 14 13 Channel output compare principle with complementary output x 0 1 2 when TIMERx is configured in compare match output mode a middle signal which is OxCPRE signal Channel x output prepare signal will be generated before the channel outputs signal The OxCPRE signal type is defined by configuring the CHxCOMCTL bit The...

Page 249: ...HCTL0 register the OxCPRE signal can be forced to 0 when the ETIFP signal derived from the external ETI pin is set to a high level The OxCPRE signal will not return to its active level until the next update event occurs Channel output complementary PWM Function of complementary is for a pair of channels CHx_O and CHx_ON the two output signals cannot be active at the same time The TIMERx has 4 chan...

Page 250: ... are configured to 1 b1 it is also necessary to configure POEN to 1 The field named DTCFG defines the dead time delay that can be used for all channels except channel 3 Refer to the TIMERx_CCHP register for details about the delay time The dead time delay insertion ensures that two complementary signals are not active at the same time When the channelx match event TIMERx counter CHxVAL occurs OxCP...

Page 251: ...nt which is generated by Clock Monitor CKM in RCU The break function is enabled by setting the BRKEN bit in the TIMERx_CCHP register The break input polarity is configured by the BRKP bit in TIMERx_CCHP register When a break occurs the POEN bit is cleared asynchronously As soon as POEN is 0 the level of the CHx_O and CHx_ON outputs are determined by the ISOx and ISOxN bits in the TIMERx_CTL1 regis...

Page 252: ...CI1FE1 only or both CI0FE0 and CI1FE1 the selection mode by setting the SMC 2 0 to 0x01 0x02 or 0x03 The mechanism for changing the counter direction is shown in Table 14 3 Counting direction in different quadrature decoder mode The quadrature decoder can be regarded as an external clock with a directional selection This means that the counter counts continuously in the interval between 0 and the ...

Page 253: ...FE0 CI1FE1 CNT_REG 19 20 18 17 16 15 16 17 18 19 20 21 TIMERx_CAR 99 Hall sensor function Hall sensor is generally used to control BLDC Motor the timers can support this function Figure 14 22 Hall sensor is used to BLDC motor show how to connect And we can see we need two timers First TIMER_in Advanced GeneralL0 TIMER should accept three HALL sensor signals Each of the three input of HALL sensors ...

Page 254: ...hip pair s timers can be selected TIMER_in TIMER2 TIMER_out TIMER0 ITI2 And so on After getting appropriate timers combination and wire connection we need to configure timers Some key settings include Enable XOR by setting TI0S then each of input signal change will make the CI0 toggle CH0VAL will record the value of counter at that moment Enable ITIx connected to commutation function directly by s...

Page 255: ...C 2 0 bits in the TIMERx_SMCFG register The input trigger of these modes can be selected by the TRGS 2 0 bits in the TIMERx_SMCFG register Table 14 4 Examples of slave mode Mode Selection Source Selection Polarity Selection Filter and Prescaler LIST SMC 2 0 3 b100 restart mode 3 b101 pause mode 3 b110 event mode TRGS 2 0 000 ITI0 001 ITI1 010 ITI2 011 ITI3 100 CI0F_ED 101 CI0FE0 If CI0FE0 or CI1FE...

Page 256: ...000 ITI0 is selected For ITI0 no polarity selector can be used For the ITI0 no filter and prescaler can be used Figure 14 24 Restart mode TIMER_CK CEN CNT_REG 94 95 96 97 98 99 0 1 2 3 4 0 1 2 UPIF ITI0 TRGIF Internal sync delay Exam2 Pause mode The counter will be paused when the trigger input is low and it will start when the trigger input is high TRGS 2 0 3 b101 CI0FE0 is selected TI0S 0 Non xo...

Page 257: ...edge can generate a pulse and then keep the CEN bit at a high state until the update event occurs or the CEN bit is written to 0 by software If the CEN bit is cleared to 0 by software the counter will be stopped and its value will be held In the single pulse mode the active edge of trigger which sets the CEN bit to 1 will enable the counter However there exists several clock delays to perform the ...

Page 258: ...master mode outputs TRGO signal to control another timer which operate in the slave mode TRGO include reset evevt start evevt update evevt capture compare pulse evevt compare evevt slave timer received the ITIx and performs the corresponding mode include internal clock mode quadrature decoder mode restart mode pause mode event mode external clock mode Figure 14 28 TIMER0 Master Slave mode timer ex...

Page 259: ..._CAR registers 3 Select the TIMER0 input trigger source from TIMER2 TRGS 010 in the TIMER0_SMCFG register 4 Configure TIMER0 in external clock mode 1 SMC 111 in TIMER0_SMCFG register 5 Start TIMER0 by writing 1 in the CEN bit TIMER0_CTL0 register 6 Start TIMER2 by writing 1 in the CEN bit TIMER2_CTL0 register Start Timer0 with Timer2 s Enable Update signal In this example we enable Timer0 with the...

Page 260: ...tart 2 timers synchronously We configure the start of TIMER0 is triggered by the enable of TIMER2 and TIMER2 is triggered by its CI0 input rises edge To ensure 2 timers start synchronously TIMER2 must be configured in Master Slave mode Do as follow 1 Configure TIMER2 slave mode to get the input trigger from CI0 TRGS 100 in the TIMER2_SMCFG register 2 Configure TIMER2 in event mode SMC 110 in the T...

Page 261: ...base address then DMA will access the TIMERx_DMATB In fact TIMERx_DMATB register is only a buffer timer will map the TIMERx_DMATB to an internal register appointed by the field of DMATA in TIMERx_DMACFG If the field of DMATC in TIMERx_DMACFG is 0 1 transfer the timer sends only one DMA request While if TIMERx_DMATC is not 0 such as 3 4 transfers then timer will send 3 more requests to DMA and DMA ...

Page 262: ...ad shadow enable 0 The shadow register for TIMERx_CAR register is disabled 1 The shadow register for TIMERx_CAR register is enabled 6 5 CAM 1 0 Counter aligns mode selection 00 No center aligned mode edge aligned mode The direction of the counter is specified by the DIR bit 01 Center aligned and counting down assert mode The counter counts under center aligned and channel is configured in output m...

Page 263: ...counter generates an overflow or underflow event 1 UPDIS Update disable This bit is used to enable or disable the update event generation 0 Update event enable When an update event occurs the corresponding shadow registers are loaded with their preloaded values These events generate update event The UPG bit is set The counter generates an overflow or underflow event The restart mode generates an u...

Page 264: ..._ON is set high This bit can be modified only when PROT 1 0 bits in TIMERx_CCHP register is 00 8 ISO0 Idle state of channel 0 output 0 When POEN bit is reset CH0_O is set low 1 When POEN bit is reset CH0_O is set high The CH0_O output changes after a dead time if CH0_ON is implemented This bit can be modified only when PROT 1 0 bits in TIMERx_CCHP register is 00 7 TI0S Channel 0 trigger input sele...

Page 265: ...t of channel x is sent 1 When update event occurs the DMA request of channel x is sent 2 CCUC Commutation control shadow register update control When the commutation control shadow enable for CHxEN CHxNEN and CHxCOMCTL bits are set CCSE 1 these shadow registers update are controlled as below 0 The shadow registers update by when CMTG bit is set 1 The shadow registers update by when CMTG bit is set...

Page 266: ...ternal clock mode 0 and external clock mode 1 are configured at the same time Note External clock mode 0 enable is in this register s SMC 2 0 bit filed 13 12 ETPSC 1 0 The prescaler of external trigger The frequency of external trigger signal ETIFP must not be at higher than 1 4 of TIMER_CK frequency When the external trigger signal is a fast clock the prescaler can be enabled to reduce ETIFP freq...

Page 267: ...ch signal is selected as the trigger input which is used to synchronize the counter 000 ITI0 001 ITI1 010 ITI2 011 ITI3 100 CI0F_ED 101 CI0FE0 110 CI1FE1 111 ETIFP These bits must not be changed when slave mode is enabled 3 OCRC OCPRE clear source selection 0 OCPRE_CLR_INT is connected to the OCPRE_CLR input 1 OCPRE_CLR_INT is connected to ETIF 2 0 SMC 2 0 Slave mode control 000 Disable mode The s...

Page 268: ... signal when CI0F_ED is selected as the trigger input the pause mode must not be used DMA and interrupt enable register TIMERx_DMAINTEN Address offset 0x0C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TRGDEN CMTDEN CH3DEN CH2DEN CH1DEN CH0DEN UPDEN BRKIE TRGIE CMTIE CH...

Page 269: ...nterrupt enable 0 disabled 1 enabled 4 CH3IE Channel 3 capture compare interrupt enable 0 disabled 1 enabled 3 CH2IE Channel 2 capture compare interrupt enable 0 disabled 1 enabled 2 CH1IE Channel 1 capture compare interrupt enable 0 disabled 1 enabled 1 CH0IE Channel 0 capture compare interrupt enable 0 disabled 1 enabled 0 UPIE Update interrupt enable 0 disabled 1 enabled Interrupt flag register...

Page 270: ...leared by software 0 No over capture interrupt occurred 1 Over capture interrupt occurred 8 Reserved Must be kept at reset value 7 BRKIF Break interrupt flag When the break input is inactive the bit is set by hardware When the break input is inactive the bit can be cleared by software 0 No active level break has been detected 1 An active level has been detected 6 TRGIF Trigger interrupt flag This ...

Page 271: ...rred 1 Update interrupt occurred Software event generation register TIMERx_SWEVG Address offset 0x14 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved BRKG TRGG CMTG CH3G CH2G CH1G CH0G UPG w w w w w w w w Bits Fields Descriptions 31 8 Reserved Must be kept at reset value 7...

Page 272: ...or compare event in channel 0 it is automatically cleared by hardware When this bit is set the CH0IF flag is set the corresponding interrupt or DMA request is sent if enabled In addition if channel 1 is configured in input mode the current value of the counter is captured in TIMERx_CH0CV register and the CH0OF flag is set if the CH0IF flag was already high 0 No generate a channel 1 capture or comp...

Page 273: ... register is reset 00 Channel 1 is programmed as output mode 01 Channel 1 is programmed as input mode IS1 is connected to CI1FE1 10 Channel 1 is programmed as input mode IS1 is connected to CI0FE1 11 Channel 1 is programmed as input mode IS1 is connected to ITS Note When CH1MS 1 0 11 it is necessary to select an internal trigger input through TRGS bits in TIMERx_SMCFG register 7 CH0COMCEN Channel ...

Page 274: ...pare output shadow enable When this bit is set the shadow register of TIMERx_CH0CV register which updates at each update event will be enabled 0 Channel 0 output compare shadow disable 1 Channel 0 output compare shadow enable The PWM mode can be used without verifying the shadow register only in single pulse mode when SPM 1 This bit cannot be modified when PROT 1 0 bit filed in TIMERx_CCHP registe...

Page 275: ...d by digital filter and this bit field configure the filtering capability Basic principle of digital filter continuously sample the CI0 input signal according to fSAMP and record the number of times of the same level of the signal After reaching the filtering capacity configured by this bit it is considered to be an effective level The filtering capability configuration is as follows CH0CAPFLT 3 0...

Page 276: ...CH2CAPPSC 1 0 rw rw rw rw rw rw Output compare mode Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 CH3COMCEN Channel 3 output compare clear enable Refer to CH0COMCEN description 14 12 CH3COMCTL 2 0 Channel 3 compare output control Refer to CH0COMCTL description 11 CH3COMSEN Channel 3 output compare shadow enable Refer to CH0COMSEN description 10 CH3COMFEN Channel 3 output c...

Page 277: ...er is equals to the output compare register TIMERx_CH2CV 100 Force low O2CPRE is forced to low level 101 Force high O2CPRE is forced to high level 110 PWM mode 0 When counting up O2CPRE is high when the counter is smaller than TIMERx_CH2CV and low otherwise When counting down O2CPRE is low when the counter is larger than TIMERx_CH2CV and high otherwise 111 PWM mode 1 When counting up O2CPRE is low...

Page 278: ...nected to CI3FE2 11 Channel 2 is programmed as input mode IS2 is connected to ITS Note When CH2MS 1 0 11 it is necessary to select an internal trigger input through TRGS bits in TIMERx_SMCFG register Input capture mode Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 12 CH3CAPFLT 3 0 Channel 3 input capture filter control Refer to CH0CAPFLT description 11 10 CH3CAPPSC 1 0 Cha...

Page 279: ...ges 11 The input capture occurs on every 8 channel input edges 1 0 CH2MS 1 0 Channel 2 mode selection Same as Output compare mode Channel control register 2 TIMERx_CHCTL2 Address offset 0x20 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CH3P CH3EN CH2NP CH2NEN CH2P CH2E...

Page 280: ...vel is active level 1 Channel 0 complementary output low level is active level When channel 0 is configured in input mode together with CH0P this bit is used to define the polarity of input signal This bit cannot be modified when PROT 1 0 bit filed in TIMERx_CCHP register is 11 or 10 2 CH0NEN Channel 0 complementary output enable When channel 0 is configured in output mode setting this bit enables...

Page 281: ...ng this bit enables CH0_O signal in active state When channel 0 is configured in input mode setting this bit enables the capture event in channel0 0 Channel 0 disabled 1 Channel 0 enabled Counter register TIMERx_CNT Address offset 0x24 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1...

Page 282: ... by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CARL 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 CARL 15 0 Counter auto reload value This bit filed specifies the auto reload value of the counter Note When the timer is configured in input capture mode this register must be configured a non zero value...

Page 283: ...5 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH0VAL 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 CH0VAL 15 0 Capture or compare value of channel0 When channel 0 is configured in input mode this bit filed indicates the counter value corresponding to the last capture event And this bit filed is read only When channel 0 is configured ...

Page 284: ... 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH2VAL 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 CH2VAL 15 0 Capture or compare value of channel 2 When channel 2 is configured in input mode this bit filed indicates the counter value corresponding to the...

Page 285: ...ress offset 0x44 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POEN OAEN BRKP BRKEN ROS IOS PROT 1 0 DTCFG 7 0 rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 POEN Primary output enable The bit can be set to 1 by Write 1 to this bit...

Page 286: ...OEN bit is set the channel output signals CHx_O CHx_ON are enabled with relationship to CHxEN CHxNEN bits in TIMERx_CHCTL2 register This bit cannot be modified when PROT 1 0 bit filed in TIMERx_CCHP register is 10 or 11 10 IOS Idle mode off state configure When POEN bit is reset this bit specifies the output state for the channels which has been configured in output mode 0 When POEN bit is reset t...

Page 287: ..._CK is the period of DTS_CK which is configured by CKDIV 1 0 in TIMERx_CTL0 2 This bit can be modified only when PROT 1 0 bit filed in TIMERx_CCHP register is 00 DMA configuration register TIMERx_DMACFG Address offset 0x48 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved D...

Page 288: ...uffer When a read or write operation is assigned to this register the register located at the address range Start Addr Transfer Timer 4 will be accessed The transfer Timer is calculated by hardware and ranges from 0 to DMATC Configuration register TIMERx_CFG Address offset 0xFC Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R...

Page 289: ...GD32E23x User Manual 289 write access ignored 0 No effect 0 OUTSEL The output value selection This bit field set and reset by software 1 If POEN and IOS is 0 the output disabled 0 No effect ...

Page 290: ... is selectable internal clock internal trigger external input external trigger Multiple counter modes up counting down counting and center aligned counting Quadrature decoder used for motion tracking and determination of both rotation direction and position Hall sensor function used for 3 phase motor control Programmable prescaler 16 bits The factor can be changed ongoing Each channel is user conf...

Page 291: ...controller APB BUS CK_TIMER CH0_IN CH1_IN CH2_IN CH3_IN CI0 ITI0 ITI1 ITI2 ITI3 ETI CAR Output Logic generation of outputs signals in compare PWM and mixed modes according to initialization software output mask and polarity control CH0_O DMA controller TIMERx_TRGO Interrupt CH1_O CH2_O CH3_O Update Trigger Cap Com DMA REQ ACK TIMERx_CH0 TIMERx_CH1 TIMERx_CH2 TIMERx_CH3 TIMERx_TG TIMERx_UP PSC PSC_...

Page 292: ...14 32 Timing chart of internal clock divided by 1 CK_TIMER CEN PSC_CLK TIMER_CK CNT_REG Reload Pulse 17 18 19 20 21 22 update event generate UPG 23 00 01 02 03 04 05 06 07 Update event UPE SMC 2 0 3 b111 external clock mode 0 External input pin source The TIMER_CK driven counter s prescaler to count can be triggered by the event of rising or falling edge on the external pin TIMERx_CH0 TIMERx_CH1 T...

Page 293: ... 33 Timing chart of PSC value change from 0 to 2 TIMER_CK CEN PSC_CLK CNT_REG Reload Pulse Prescaler CNT Prescaler shadow 94 95 96 97 98 99 0 2 0 2 0 1 2 0 1 2 0 1 PSC value UPG 0 2 0 1 2 Counter up counting In this mode the counter counts up continuously from 0 to the counter reload value which is defined in the TIMERx_CAR register in a count up direction Once the counter reaches the counter relo...

Page 294: ...unting mode change TIMERx_CAR on the go show some examples of the counter behavior for different clock prescaler factor when TIMERx_CAR 0x99 Figure 14 34 Timing chart of up counting mode PSC 0 2 CEN PSC_CLK CNT_REG 94 95 96 97 98 99 0 1 2 3 4 5 6 7 Update event UPE Update interrupt flag UPIF CNT_REG 96 Update event UPE Update interrupt flag UPIF Hardware set Software clear Hardware set PSC 0 PSC 2...

Page 295: ...register in a count down direction Once the counter reaches to 0 the counter will start counting down from the counter reload value The counting direction bit DIR in the TIMERx_CTL0 register should be set to 1 for the down counting mode When the update event is set by the UPG bit in the TIMERx_SWEVG register the counter value will be initialized to the counter reload value and an update event will...

Page 296: ...LK 2 1 0 99 98 Figure 14 37 Timing chart of down counting mode change TIMERx_CAR on the go TIMER_CK CEN PSC_CLK CNT_REG 5 4 3 2 1 0 99 98 97 96 95 94 93 92 Update event UPE Update interrupt flag UPIF Auto reload register 120 99 change CAR Vaule CNT_REG 5 4 3 2 1 0 99 1 0 120 Update event UPE Update interrupt flag UPIF Auto reload register 120 99 change CAR Vaule 120 99 Auto reload shadow register ...

Page 297: ...TIMERx_SWEVG register will initialize the counter value to 0 and generate an update event irrespective of whether the counter is counting up or down in the center aligned counting mode The UPIF bit in the TIMERx_INTF register will be set to 1 either when an underflow event or an overflow event occurs While the CHxIF bit is associated with the value of CAM in TIMERx_CTL0 The details refer to Figure...

Page 298: ...s or compare match outputs Each channel is built around a channel capture compare register including an input stage channel controller and an output stage Channel input capture function Channel input capture function allows the channel to perform measurements such as pulse timing frequency period duty cycle and so on The input stage consists of a digital filter a channel polarity selection edge de...

Page 299: ...gnal of other channel or the internal trigger signal by configuring CHxMS bits The IC prescaler makes several input events generate one effective capture event On the capture event TIMERx_CHxCV will store the value of counter So the process can be divided into several steps as below Step1 Filter configuration CHxCAPFLT in TIMERx_CHCTL0 Based on the input signal and quality of requested signal conf...

Page 300: ...Hx_O CNT CHxCV CNT CHxCV CNT CHxCV Figure 14 40 Channel output compare principle x 0 1 2 3 shows the logic circuit of output compare mode The relationship between the channel output signal CHx_O and the OxCPRE signal more details refer to Channel output prepare signal is described as blew The active level of O0CPRE is high the output level of CH0_O depends on OxCPRE signal CHxP bit and CH0P bit pl...

Page 301: ... below shows the three compare modes toggle set clear CAR 0x63 CHxVAL 0x3 Figure 14 41 Output compare under three modes CEN CNT_REG 00 01 02 03 04 05 62 63 Overflow match toggle CNT_CLK OxCPRE 00 01 02 03 04 05 62 63 01 02 03 04 05 00 match set match clear OxCPRE OxCPRE Output PWM function In the output PWM function by setting the CHxCOMCTL bit to 3 b110 PWM mode 0 or to 3 b 111 PWM mode 1 the cha...

Page 302: ...APWM shows the CAPWM output and interrupts waveform In up counting mode if the value of TIMERx_CHxCV is greater than the value of TIMERx_CAR the output will be always inactive in PWM mode 0 CHxCOMCTL 3 b110 And if the value of TIMERx_CHxCV is greater than the value of TIMERx_CAR the output will be always active in PWM mode 1 CHxCOMCTL 3 b111 Figure 14 42 Timing chart of EAPWM 0 CHxVAL CAR PWM MODE...

Page 303: ... setting to high by configuring the CHxCOMCTL field to 0x01 setting to low by configuring the CHxCOMCTL field to 0x02 or toggling signal by configuring the CHxCOMCTL field to 0x03 when the counter value matches the content of the TIMERx_CHxCV register The PWM mode 0 PWM mode 1 output is another output type of OxCPRE which is setup by configuring the CHxCOMCTL field to 0x06 0x07 In these modes the ...

Page 304: ...TIMERx will send a request to DMA when the interrupt event occurs DMA is configured to M2P memory to peripheral mode and the address of TIMERx_DMATB is configured to PADDR peripheral base address then DMA will access the TIMERx_DMATB In fact TIMERx_DMATB register is only a buffer timer will map the TIMERx_DMATB to an internal register appointed by the field of DMATA in TIMERx_DMACFG If the field o...

Page 305: ...ad shadow enable 0 The shadow register for TIMERx_CAR register is disabled 1 The shadow register for TIMERx_CAR register is enabled 6 5 CAM 1 0 Counter aligns mode selection 00 No center aligned mode edge aligned mode The direction of the counter is specified by the DIR bit 01 Center aligned and counting down assert mode The counter counts under center aligned and channel is configured in output m...

Page 306: ...counter generates an overflow or underflow event 1 UPDIS Update disable This bit is used to enable or disable the update event generation 0 Update event enable When an update event occurs the corresponding shadow registers are loaded with their preloaded values These events generate update event The UPG bit is set The counter generates an overflow or underflow event The restart mode generates an u...

Page 307: ...rt event occurs a TRGO trigger signal is output The counter start source CEN control bit is set The trigger input in pause mode is high 010 When an update event occurs a TRGO trigger signal is output The update source depends on UPDIS bit and UPS bit 011 When a capture or compare pulse event occurs in channel0 a TRGO trigger signal is output 100 When a compare event occurs a TRGO trigger signal is...

Page 308: ... When the slave mode is configured as restart mode pause mode or event mode the timer can still work in the external clock 1 mode by setting this bit But the TRGS bits must not be 3 b111 in this case The clock source of the timer will be ETIFP if external clock mode 0 and external clock mode 1 are configured at the same time Note External clock mode 0 enable is in this register s SMC 2 0 bit filed...

Page 309: ...101 5 fDTS_CK 32 4 b1110 6 4 b1111 8 7 MSM Master slave mode This bit can be used to synchronize selected timers to begin counting at the same time The TRGI is used as the start event and through TRGO timers are connected together 0 Master slave mode disable 1 Master slave mode enable 6 4 TRGS 2 0 Trigger selection This bit field specifies which signal is selected as the trigger input which is use...

Page 310: ...10 Event Mode A rising edge of the trigger input enables the counter 111 External Clock Mode 0 The counter counts on the rising edges of the selected trigger Because CI0F_ED outputs 1 pulse for each transition on CI0F and the pause mode checks the level of the trigger signal when CI0F_ED is selected as the trigger input the pause mode must not be used DMA and interrupt enable register TIMERx_DMAIN...

Page 311: ...E Trigger interrupt enable 0 disabled 1 enabled 5 Reserved Must be kept at reset value 4 CH3IE Channel 3 capture compare interrupt enable 0 disabled 1 enabled 3 CH2IE Channel 2 capture compare interrupt enable 0 disabled 1 enabled 2 CH1IE Channel 1 capture compare interrupt enable 0 disabled 1 enabled 1 CH0IE Channel 0 capture compare interrupt enable 0 disabled 1 enabled 0 UPIE Update interrupt e...

Page 312: ... cleared by software 0 No over capture interrupt occurred 1 Over capture interrupt occurred 8 7 Reserved Must be kept at reset value 6 TRGIF Trigger interrupt flag This flag is set on trigger event and cleared by software When in pause mode both edges on trigger input generates a trigger event otherwise only an active edge on trigger input can generates a trigger event 0 No trigger event occurred ...

Page 313: ... 6 TRGG Trigger event generation This bit is set by software and cleared by hardware automatically When this bit is set the TRGIF flag in TIMERx_STAT register is set related interrupt or DMA transfer can occur if enabled 0 No generate a trigger event 1 Generate a trigger event 5 Reserved Must be kept at reset value 4 CH3G Channel 3 s capture or compare event generation Refer to CH0G description 3 ...

Page 314: ... to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH1COM CEN CH1COMCTL 2 0 CH1COM SEN CH1COM FEN CH1MS 1 0 CH0COM CEN CH0COMCTL 2 0 CH0COM SEN CH0COM FEN CH0MS 1 0 CH1CAPFLT 3 0 CH1CAPPSC 1 0 CH0CAPFLT 3 0 CH0CAPPSC 1 0 Rw rw rw rw rw rw Output compare mode Bits Fields Descriptions 31 16 Reserved Must be kept at reset valu...

Page 315: ...ter is equals to the output compare register TIMERx_CH0CV 010 Clear the channel output O0CPRE signal is forced low when the counter is equals to the output compare register TIMERx_CH0CV 011 Toggle on match O0CPRE toggles when the counter is equals to the output compare register TIMERx_CH0CV 100 Force low O0CPRE is forced to low level 101 Force high O0CPRE is forced to high level 110 PWM mode0 When...

Page 316: ...d as output mode 01 Channel 0 is programmed as input mode IS0 is connected to CI0FE0 10 Channel 0 is programmed as input mode IS0 is connected to CI1FE0 11 Channel 0 is programmed as input mode IS0 is connected to ITS Note When CH0MS 1 0 11 it is necessary to select an internal trigger input through TRGS bits in TIMERx_SMCFG register Input capture mode Bits Fields Descriptions 31 16 Reserved Must ...

Page 317: ...hannel input edge 01 The input capture occurs on every 2 channel input edges 10 The input capture occurs on every 4 channel input edges 11 The input capture occurs on every 8 channel input edges 1 0 CH0MS 1 0 Channel 0 mode selection Same as Output compare mode Channel control register 1 TIMERx_CHCTL1 Address offset 0x1C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30...

Page 318: ...gger input is selected through TRGS bits in TIMERx_SMCFG register 7 CH2COMCEN Channel 2 output compare clear enable When this bit is set if the ETIFP signal is detected as high level the O2CPRE signal will be cleared 0 Channel 2 output compare clear disable 1 Channel 2 output compare clear enable 6 4 CH2COMCTL 2 0 Channel 2 compare output control This bit field specifies the compare output mode of...

Page 319: ...gle pulse mode when SPM 1 This bit cannot be modified when PROT 1 0 bit filed in TIMERx_CCHP register is 11 and CH0MS bit filed is 00 2 CH2COMFEN Channel 2 output compare fast enable When this bit is set the effect of an event on the trigger in input on the capture compare output will be accelerated if the channel is configured in PWM1 or PWM2 mode The output channel will treat an active edge on t...

Page 320: ...onfigured by this bit it is considered to be an effective level The filtering capability configuration is as follows CH2CAPFLT 3 0 Times fSAMP 4 b0000 Filter disabled 4 b0001 2 fCK_TIMER 4 b0010 4 4 b0011 8 4 b0100 6 fDTS 2 4 b0101 8 4 b0110 6 fDTS 4 4 b0111 8 4 b1000 6 fDTS 8 4 b1001 8 4 b1010 5 fDTS 16 4 b1011 6 4 b1100 8 4 b1101 5 fDTS 32 4 b1110 6 4 b1111 8 3 2 CH2CAPPSC 1 0 Channel 2 input ca...

Page 321: ...ept at reset value 13 CH3P Channel 3 capture compare function polarity Refer to CH0P description 12 CH3EN Channel 3 capture compare function enable Refer to CH0EN description 11 CH2NP Channel 2 complementary output polarity Refer to CH0NP description 10 Reserved Must be kept at reset value 9 CH2P Channel 2 capture compare function polarity Refer to CH0P description 8 CH2EN Channel 2 capture compar...

Page 322: ...r capture or trigger operation in slave mode And CIxFE0 will not be inverted CH0NP 0 CH0P 1 CIxFE0 s falling edge is the active signal for capture or trigger operation in slave mode And CIxFE0 will be inverted CH0NP 1 CH0P 0 Reserved CH0NP 1 CH0P 1 CIxFE0 s falling and rising edge are both the active signal for capture or trigger operation in slave mode And CIxFE0 will be not inverted This bit can...

Page 323: ... 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 PSC 15 0 Prescaler value of the counter clock The TIMER_CK clock is divided by PSC 1 to generate the counter clock The value of this bit filed will be loaded to the corresponding shadow register at every update event Counter auto reload register TIMERx_CAR Address offset 0x2C Reset value 0x0000 0000 This register has to...

Page 324: ...ept at reset value 15 0 CH0VAL 15 0 Capture or compare value of channel0 When channel 0 is configured in input mode this bit filed indicates the counter value corresponding to the last capture event And this bit filed is read only When channel 0 is configured in output mode this bit filed contains value to be compared to the counter When the corresponding shadow register is enabled the shadow regi...

Page 325: ...7 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH2VAL 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 CH2VAL 15 0 Capture or compare value of channel 2 When channel 2 is configured in input mode this bit filed indicates the counter value corresponding to the last capture event And this bit filed is read only When channel 2 is configured in output mode this bit...

Page 326: ...5 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DMATC 4 0 Reserved DMATA 4 0 rw rw Bits Fields Descriptions 31 13 Reserved Must be kept at reset value 12 8 DMATC 4 0 DMA transfer count This filed defines the number n of the register that DMA will access R W n DMATC 4 0 1 DMATC 4 0 is from 5 b0_0000 to 5 b1_0001 7 5 Reserved Must be kept at reset value 4 0 DMATA 4 0 DMA transfer access start address ...

Page 327: ...and ranges from 0 to DMATC Configuration register TIMERx_CFG Address offset 0xFC Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CHVSEL Reserved rw Bits Fields Descriptions 31 2 Reserved Must be kept at reset value 1 CHVSEL Write CHxVAL register selection This bit field s...

Page 328: ...mers can be programmed and be used for counting their external events can be used to drive other timers 14 3 2 Characteristics Total channel num 1 Counter width 16 bits Source of count clock internal clock Counter mode count up only Programmable prescaler 16 bits Factor can be changed ongoing Each channel is user configurable Input capture mode output compare mode programmable PWM mode Auto reload...

Page 329: ...essor Trigger Selector Counter Counter TIMERx_CHxCV Register Interrupt Register set and update Interrupt collector APB BUS CK_TIMER CH0_IN CI0 CAR Output Logic generation of outputs signals in compare PWM and mixed modes according to initialization software output mask and polarity control CH0_O Interrupt Update Cap Com PSC TIMER_CK PSC_CLK ...

Page 330: ... to generate PSC_CLK The TIMER_CK driven counter s prescaler to count is equal to CK_TIMER which is from RCU Figure 14 45 Timing chart of internal clock divided by 1 CK_TIMER CEN PSC_CLK TIMER_CK CNT_REG Reload Pulse 17 18 19 20 21 22 update event generate UPG 23 00 01 02 03 04 05 06 07 Update event UPE Clock prescaler The counter clock PSC_CK is obtained by the TIMER_CK through the prescaler and ...

Page 331: ...r will start counting up from 0 again The update event is generated at each counter overflow The counting direction bit DIR in the TIMERx_CTL1 register should be set to 0 for the up counting mode When the update event is set by the UPG bit in the TIMERx_SWEVG register the counter value will be initialized to 0 and generates an update event If the UPDIS bit in TIMERx_CTL0 register is set the update...

Page 332: ... 8 PSC_CLK 97 98 99 0 1 Figure 14 48 Timing chart of up counting mode change TIMERx_CAR on the go TIMER_CK CEN PSC_CLK CNT_REG 94 95 96 97 98 99 0 1 2 3 4 5 6 7 Update event UPE Update interrupt flag UPIF Auto reload register 120 99 change CAR Vaule CNT_REG 113 114 115 116 117 118 119 120 0 1 2 98 99 0 Update event UPE Update interrupt flag UPIF Auto reload register 120 99 change CAR Vaule 120 99 ...

Page 333: ...e CI0 Synchronizer D presclare Capture Register CH0VAL Clock Processer Counter TIMER_CK Q Filter D Q D Q Edge Detector ITS CH0MS CH0IF CH0IE CH0_CC_I TIMERx_CC_INT Capture INT From Other Channal CH0CAPPSC Edge selector inverter Based on CH0P CH0NP CI0FE0 Rising Falling ITI0 ITI3 ITI1 ITI2 CI0FED Rising Falling IS0 CI0FED First the input signal of channel CIx is synchronized to TIMER_CK signal and ...

Page 334: ...lect CI0 as channel 0 capture signals by setting CH0MS to 2 b01 in the channel control register TIMERx_CHCTL0 and set capture on rising edge The counter is set to restart mode and is restarted on channel 0 rising edge Then the TIMERX_CH0CV can measure the PWM period Channel output compare function Figure 14 50 Channel output compare principle Capture compare register CH0CV Counter output comparato...

Page 335: ...source clock prescaler and so on Step2 Compare mode configuration Set the shadow enable mode by CHxCOMSEN Set the output mode set clear toggle by CHxCOMCTL Select the active polarity by CHxP Enable the output by CHxEN Step3 Interrupt DMA request enables configuration by CHxIE Step4 Compare output timing configuration by TIMERx_CAR and TIMERx_CHxCV The TIMERx_CHxCV can be changed onging to meet the...

Page 336: ...nal As is shown in Figure 14 50 Channel output compare principle when TIMERx is configured in compare match output mode a middle signal which is OxCPRE signal Channel x output prepare signal will be generated before the channel outputs signal The OxCPRE signal type is defined by configuring the CHxCOMCTL bit The OxCPRE signal has several types of output function These include keeping the original ...

Page 337: ...ced output which can be achieved by configuring the CHxCOMCTL field to 0x04 0x05 The output can be forced to an inactive active level irrespective of the comparison condition between the values of the counter and the TIMERx_CHxCV Timer debug mode When the Cortex M23 halted and the TIMERx_HOLD configuration bit in DBG_CTL0 register set to 1 the TIMERx counter stops ...

Page 338: ...CK_TIMER 2 10 fDTS fCK_TIMER 4 11 Reserved 7 ARSE Auto reload shadow enable 0 The shadow register for TIMERx_CAR register is disabled 1 The shadow register for TIMERx_CAR register is enabled 6 3 Reserved Must be kept at reset value 2 UPS Update source This bit is used to select the update event sources by software 0 These events generate update interrupts or DMA requests The UPG bit is set The cou...

Page 339: ...ode and encoder mode Interrupt enable register TIMERx_DMAINTEN Address offset 0x0C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CH0IE UPIE rw rw Bits Fields Descriptions 31 2 Reserved Must be kept at reset value 1 CH0IE Channel 0 capture compare interrupt enable 0 disa...

Page 340: ...e and cleared by software When channel 0 is in input mode this flag is set when a capture event occurs When channel 0 is in output mode this flag is set when a compare event occurs 0 No Channel 1 interrupt occurred 1 Channel 1 interrupt occurred 0 UPIF Update interrupt flag This bit is set by hardware on an update event and cleared by software 0 No update interrupt occurred 1 Update interrupt occu...

Page 341: ...2 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Reserved CH0COMCTL 2 0 CH0COM SEN CH0COM FEN CH0MS 1 0 CH0CAPFLT 3 0 CH0CAPPSC 1 0 rw rw rw Output compare mode Bits Fields Descriptions 31 7 Reserved Must be kept at reset value 6 4 CH0COMCTL 2 0 Channel 0 compare output control This bit field specifies the compare output mode of the the ...

Page 342: ...w register only in single pulse mode when SPM 1 This bit cannot be modified when PROT 1 0 bit filed in TIMERx_CCHP register is 11 and CH0MS bit filed is 00 2 CH0COMFEN Channel 0 output compare fast enable When this bit is set the effect of an event on the trigger in input on the capture compare output will be accelerated if the channel is configured in PWM0 or PWM1 mode The output channel will tre...

Page 343: ...00 6 fDTS 2 4 b0101 8 4 b0110 6 fDTS 4 4 b0111 8 4 b1000 6 fDTS 8 4 b1001 8 4 b1010 5 fDTS 16 4 b1011 6 4 b1100 8 4 b1101 5 fDTS 32 4 b1110 6 4 b1111 8 3 2 CH0CAPPSC 1 0 Channel 0 input capture prescaler This bit field specifies the factor of the prescaler on channel 0 input The prescaler is reset when CH0EN bit in TIMERx_CHCTL2 register is clear 00 Prescaler disable input capture occurs on every ...

Page 344: ...el is active level When channel 0 is configured in input mode this bit specifies the CI0 signal polarity CH0NP CH0P will select the active trigger or capture polarity for CI0FE0 or CI1FE0 CH0NP 0 CH0P 0 CIxFE0 s rising edge is the active signal for capture or trigger operation in slave mode And CIxFE0 will not be inverted CH0NP 0 CH0P 1 CIxFE0 s falling edge is the active signal for capture or tri...

Page 345: ...rescaler register TIMERx_PSC Address offset 0x28 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PSC 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 PSC 15 0 Prescaler value of the counter clock The TIMER_CK clock is divided by PSC 1 to generate th...

Page 346: ...s register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH0VAL 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 CH0VAL 15 0 Capture or compare value of channel0 When channel 0 is configured in input mode this bit filed indicates the counter value corresponding to the last capture eve...

Page 347: ...k 11 Channel 0 input is connected to CKOUTSEL Configuration register TIMERx_CFG Address offset 0xFC Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CHVSEL Reserved rw rw Bits Fields Descriptions 31 2 Reserved Must be kept at reset value 1 CHVSEL Write CHxVAL register sele...

Page 348: ...ters incrementing in unison 14 4 2 Characteristics Total channel num 2 Counter width 16 bits Clock source of timer is selectable internal clock internal trigger external input Counter modes count up only Programmable prescaler 16 bits The factor can be changed ongoing Each channel is user configurable input capture mode output compare mode programmable PWM mode single pulse mode Programmable dead ...

Page 349: ...es according to initialization complementary mode software output control deadtime insertion break input output mask and polarity control BRKEN BRKIN CKM clock monitor CH0_O CH0_ON DMA controller TIMERx_TRGO DMA REQ ACK TIMERx_CH0 TIMERx_CH1 TIMERx_TG TIMERx_UP Interrupt break update trig ctrl cap com CH1_O req en direct req set PSC PSC_CLK TIMER_CK 14 4 4 Function overview Clock source configurat...

Page 350: ...EN PSC_CLK TIMER_CK CNT_REG Reload Pulse 17 18 19 20 21 22 update event generate UPG 23 00 01 02 03 04 05 06 07 Update event UPE SMC 2 0 3 b111 external clock mode 0 External input pin is selected as timer clock source The TIMER_CK which drives counter s prescaler to count can be triggered by the event of rising or falling edge on the external pin TIMERx_CH0 TIMERx_CH1 This mode can be selected by...

Page 351: ...ated In addition the update events will be generated after TIMERx_CREP 1 times of overflow events The counting direction bit DIR in the TIMERx_CTL0 register should be set to 0 for the up counting mode Whenever if the update event software trigger is enabled by setting the UPG bit in the TIMERx_SWEVG register the counter value will be initialized to 0 and generates an update event If set the UPDIS ...

Page 352: ... 8 PSC_CLK 97 98 99 0 1 Figure 14 57 Timing chart of up counting mode change TIMERx_CAR on the go TIMER_CK CEN PSC_CLK CNT_REG 94 95 96 97 98 99 0 1 2 3 4 5 6 7 Update event UPE Update interrupt flag UPIF Auto reload register 120 99 change CAR Vaule CNT_REG 113 114 115 116 117 118 119 120 0 1 2 98 99 0 Update event UPE Update interrupt flag UPIF Auto reload register 120 99 change CAR Vaule 120 99 ...

Page 353: ...Overflow TIMERx_CREP 0x0 TIMER_CK 0 1 98 99 0 1 UPIF TIMERx_CREP 0x1 98 99 0 1 98 99 0 1 UPIF UPIF TIMERx_CREP 0x2 PSC_CLK Input capture and output compare channels The general level3 timer has two independent channels which can be used as capture inputs or compare match outputs Each channel is built around a channel capture compare register including an input stage channel controller and an outpu...

Page 354: ...erate one effective capture event On the capture event CHxVAL will restore the value of Counter So the process can be divided to several steps as below Step1 Filter configuration CHxCAPFLT in TIMERx_CHCTL0 Based on the input signal and requested signal quality configure compatible CHxCAPFLT Step2 Edge selection CHxP CHxNP in TIMERx_CHCTL2 Rising or falling edge choose one by CHxP CHxNP Step3 Captu...

Page 355: ...trol CH0COMCTL CNT CH0CV CNT CH0CV CNT CH0CV Output complementary protection register Dead Time Output enable and polarity selector CH0P CH0NP CH0E CH0NE O0CPRE CH0_O CH0_ON Figure 14 61 Channel output compare principle CH1_O Capture compare register CH1CV Counter output comparator Compare output control CH1COMCTL Output enable and polarity selector CH1P CH1E O1CPRE CH1_O CNT CH1CV CNT CH1CV CNT C...

Page 356: ...es the value in the CHxVAL register of an output compare channel the channel n output can be set cleared or toggled based on CHxCOMCTL When the counter reaches the value in the CHxVAL register the CHxIF bit is set and the channel n interrupt is generated if CHxIE 1 And the DMA request will be assert if CHxDEN 1 So the process can be divided to several steps as below Step1 Clock Configuration Such ...

Page 357: ...mode0 or to 3 b 111 PWM mode1 the channel can generate PWM waveform according to the TIMERx_CAR registers and TIMERx_CHxCV registers The period is determined by TIMERx_CAR and duty cycle is determined by TIMERx_CHxCV Figure 14 63 PWM mode timechart shows the PWM output mode and interrupts waveform If TIMERx_CHxCV is greater than TIMERx_CAR the output will be always active under PWM mode0 CHxCOMCTL...

Page 358: ...RE signal level is changed according to the counting direction and the relationship between the counter value and the TIMERx_CHxCV content With regard to a more detail description refer to the relative bit definition Another special function of the OxCPRE signal is a forced output which can be achieved by setting the CHxCOMCTL field to 0x04 0x05 Here the output can be forced to an inactive active ...

Page 359: ...clock is enable CHx_O ISOx CHx_ON ISOxN 1 0 1 1 0 0 1 0 0 CHx_O CHx_ON LOW CHx_O CHx_ON output disable 1 CHx_O LOW CHx_O output disable CHx_ON OxCPRE CHxNP CHx_ON output enable 1 0 CHx_O OxCPRE CHxP CHx_O output enable CHx_ON LOW CHx_ON output disable 1 CHx_O OxCPRE CHxP CHx_O output enable CHx_ON OxCPRE CHxNP CHx_ON output enable 1 0 0 CHx_O CHxP CHx_O output disable CHx_ON CHxNP CHx_ON output di...

Page 360: ...t B when counter match counter CHxVAL occurs again OxCPRE is cleared CHx_O signal will be cleared at once while CHx_ON signal remains at the low value until the end of the dead time delay Sometimes we can see corner cases about the dead time insertion For example The dead time delay is greater than or equal to the CHx_O duty cycle then the CHx_O signal is always the inactive value as show in the F...

Page 361: ...reset state and then the dead time generator is reactivated in order to drive the outputs with the level programmed in the ISOx and ISOxN bits after a dead time When a break occurs the BRKIF bit in the TIMERx_INTF register is set If BRKIE is 1 an interrupt generated Figure 14 65 Output behavior in response to a break The break high active OxCPRE CHx_O CHx_ON BRKIN CHx_O CHx_ON CHx_O CHx_ON ISOx IS...

Page 362: ...e used For the CIx configure Filter by CHxCAPFLT no prescaler can be used Exam1 Restart mode The counter can be clear and restart when a rising trigger input TRGS 2 0 3 b 000 ITI0 is the selection For ITI0 no polarity selector can be used For the ITI0 no filter and prescaler can be used Figure 14 66 Restart mode TIMER_CK CEN CNT_REG 94 95 96 97 98 99 0 1 2 3 4 0 1 2 UPIF ITI0 TRGIF Internal sync d...

Page 363: ...ting SPM in TIMERx_CTL0 When you set SPM the counter will be clear and stop when the next update event In order to get pulse waveform you can set the TIMERx to PWM mode or compare by CHxCOMCTL Once the timer is set to operate in the single pulse mode it is not necessary to set the timer enable bit CEN in the TIMERx_CTL0 register to 1 to enable the counter The trigger to generate a pulse can be sou...

Page 364: ... TIMERx_CHxCV 4 TIMERx_CAR 99 TIMER_CK PSC_CLK CEN CNT_REG 0 1 2 3 4 5 98 99 00 O0CPRE CI1 Under SPM counter stop Timers interconnection Refer to Timers interconnection Timer DMA mode Timer s DMA mode is the function that configures timer s register by DMA module The relative registers are TIMERx_DMACFG and TIMERx_DMATB Of course you have to enable a DMA request which will be asserted by some inte...

Page 365: ...365 If one more time DMA request event coming TIMERx will repeat the process as above Timer debug mode When the Cortex M23 halted and the TIMERx_HOLD configuration bit in DBG_CTL1 register set to 1 the TIMERx counter stops ...

Page 366: ... and digital filter sample clock DTS 00 fDTS fCK_TIMER 01 fDTS fCK_TIMER 2 10 fDTS fCK_TIMER 4 11 Reserved 7 ARSE Auto reload shadow enable 0 The shadow register for TIMERx_CAR register is disabled 1 The shadow register for TIMERx_CAR register is enabled 6 4 Reserved Must be kept at reset value 3 SPM Single pulse mode 0 Single pulse mode disable The counter continues after update event 1 Single pu...

Page 367: ...enable 0 Counter disable 1 Counter enable The CEN bit must be set by software when timer works in external clock pause mode and encoder mode Control register 1 TIMERx_CTL1 Address offset 0x04 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved ISO1 ISO0N ISO0 Reserved MMC 2 0...

Page 368: ...ure or compare pulse event occurs in channel0 a TRGO trigger signal is output 100 When a compare event occurs a TRGO trigger signal is output The compare source is from O0CPRE 101 When a compare event occurs a TRGO trigger signal is output The compare source is from O1CPRE 110 Reserved 111 Reserved 3 DMAS DMA request source selection 0 When capture or compare event occurs the DMA request of channe...

Page 369: ...er slave mode This bit can be used to synchronize selected timers to begin counting at the same time The TRGI is used as the start event and through TRGO timers are connected together 0 Master slave mode disable 1 Master slave mode enable 6 4 TRGS 2 0 Trigger selection This bit field specifies which signal is selected as the trigger input which is used to synchronize the counter 000 ITI0 001 ITI1 ...

Page 370: ...of the trigger signal when CI0F_ED is selected as the trigger input the pause mode must not be used DMA and interrupt enable register TIMERx_DMAINTEN Address offset 0x0C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TRGDEN CMTDEN Reserved CH1DEN CH0DEN UPDEN BRKIE TRGIE...

Page 371: ...pare interrupt enable 0 disabled 1 enabled 1 CH0IE Channel 0 capture compare interrupt enable 0 disabled 1 enabled 0 UPIE Update interrupt enable 0 disabled 1 enabled Interrupt flag register TIMERx_INTF Address offset 0x10 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved C...

Page 372: ... mode both edges on trigger input generates a trigger event otherwise only an active edge on trigger input can generates a trigger event 0 No trigger event occurred 1 Trigger interrupt occurred 5 CMTIF Channel commutation interrupt flag This flag is set by hardware when channel s commutation event occurs and cleared by software 0 No channel commutation interrupt occurred 1 Channel commutation inte...

Page 373: ...d 0 No generate a break event 1 Generate a break event 6 TRGG Trigger event generation This bit is set by software and cleared by hardware automatically When this bit is set the TRGIF flag in TIMERx_INTF register is set related interrupt or DMA transfer can occur if enabled 0 No generate a trigger event 1 Generate a trigger event 5 CMTG Channel commutation event generation This bit is set by softw...

Page 374: ... value The prescaler counter is cleared at the same time 0 No generate an update event 1 Generate an update event Channel control register 0 TIMERx_CHCTL0 Address offset 0x18 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CH1COMCTL 2 0 CH1COM SEN CH1COM FEN CH1MS 1 0 Res...

Page 375: ... output compare register TIMERx_CH0CV 011 Toggle on match O0CPRE toggles when the counter is equals to the output compare register TIMERx_CH0CV 100 Force low O0CPRE is forced to low level 101 Force high O0CPRE is forced to high level 110 PWM mode0 When counting up O0CPRE is high when the counter is smaller than TIMERx_CH0CV and low otherwise When counting down O0CPRE is low when the counter is lar...

Page 376: ...put mode IS0 is connected to CI1FE0 11 Channel 0 is programmed as input mode IS0 is connected to ITS Note When CH0MS 1 0 11 it is necessary to select an internal trigger input through TRGS bits in TIMERx_SMCFG register Input capture mode Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 12 CH1CAPFLT 3 0 Channel 1 input capture filter control Refer to CH0CAPFLT description 11 1...

Page 377: ...ture occurs on every 2 channel input edges 10 The input capture occurs on every 4 channel input edges 11 The input capture occurs on every 8 channel input edges 1 0 CH0MS 1 0 Channel 0 mode selection Same as Output compare mode Channel control register 2 TIMERx_CHCTL2 Address offset 0x20 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 ...

Page 378: ...re compare function polarity When channel 0 is configured in output mode this bit specifies the output signal polarity 0 Channel 0 high level is active level 1 Channel 0 low level is active level When channel 0 is configured in input mode this bit specifies the CI0 signal polarity CH0NP CH0P will select the active trigger or capture polarity for CI0FE0 or CI1FE0 CH0NP 0 CH0P 0 CIxFE0 s rising edge...

Page 379: ...e current counter value Writing to this bit filed can change the value of the counter Prescaler register TIMERx_PSC Address offset 0x28 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PSC 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 PSC 15 0 Pre...

Page 380: ...ster TIMERx_CREP Address offset 0x30 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CREP 7 0 rw Bits Fields Descriptions 31 8 Reserved Must be kept at reset value 7 0 CREP 7 0 Counter repetition value This bit filed specifies the update event generation rate Each time th...

Page 381: ...ng shadow register is enabled the shadow register updates every update event Channel 1 capture compare value register TIMERx_CH1CV Address offset 0x38 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH1VAL 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value...

Page 382: ...put mode setting this bit enables the channel outputs CHx_O and CHx_ON if the corresponding enable bits CHxEN CHxNEN in TIMERx_CHCTL2 register have been set 0 Disable channel outputs CHxO or CHxON 1 Enabled channel outputs CHxO or CHxON Note This bit is only valid when CHxMS 2 b00 14 OAEN Output automatic enable 0 The POEN bit can only be set by software 1 POEN can be set at the next update event ...

Page 383: ...ROT 1 0 Complementary register protect control This bit filed specifies the write protection property of registers 00 protect disable No write protection 01 PROT mode 0 The ISOx ISOxN bits in TIMERx_CTL1 register and the BRKEN BRKP OAEN DTCFG bits in TIMERx_CCHP register are writing protected 10 PROT mode 1 In addition of the registers in PROT mode 0 the CHxP CHxNP bits in TIMERx_CHCTL2 register i...

Page 384: ... number n of the register that DMA will access R W n DMATC 4 0 1 DMATC 4 0 is from 5 b0_0000 to 5 b1_0001 7 5 Reserved Must be kept at reset value 4 0 DMATA 4 0 DMA transfer access start address This filed define the first address for the DMA access the TIMERx_DMATB When access is done through the TIMERx_DMA address first time this bit field specifies the address you just access And then the secon...

Page 385: ...et 0xFC Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CHVSEL OUTSEL rw rw Bits Fields Descriptions 31 2 Reserved Must be kept at reset value 1 CHVSEL Write CHxVAL register selection This bit field set and reset by software 1 If write the CHxVAL register the write value ...

Page 386: ...ludes a dead time Insertion module which is suitable for motor control applications 14 5 2 Characteristics Total channel num 1 Counter width 16 bits Clock source of counter clock internal clock Counter modes count up only Programmable prescaler 16 bits The factor can be changed ongoing Each channel is user configurable input capture mode output compare mode programmable PWM mode single pulse mode ...

Page 387: ...of outputs signals in compare PWM and mixed modes according to initialization complementary mode software output control deadtime insertion break input output mask and polarity control BRKEN BRKIN CKM clock monitor CH0_O CH0_ON DMA controller DMA REQ ACK TIMERx_CH0 TIMERx_UP cap com req en direct req set PSC PSC_CLK TIMER_CK Interrupt break update 14 5 4 Function overview Clock source configuratio...

Page 388: ...TIMER which is from RCU Figure 14 71 Timing chart of internal clock divided by 1 CK_TIMER CEN PSC_CLK TIMER_CK CNT_REG Reload Pulse 17 18 19 20 21 22 update event generate UPG 23 00 01 02 03 04 05 06 07 Update event UPE Clock prescaler The counter clock PSC_CK is obtained by the TIMER_CK through the prescaler and the prescale factor can be configured from 1 to 65536 through the prescaler register ...

Page 389: ... In addition the update events will be generated after TIMERx_CREP 1 times of overflow events The counting direction bit DIR in the TIMERx_CTL0 register should be set to 0 for the up counting mode Whenever if the update event software trigger is enabled by setting the UPG bit in the TIMERx_SWEVG register the counter value will be initialized to 0 and generates an update event If set the UPDIS bit ...

Page 390: ... 8 PSC_CLK 97 98 99 0 1 Figure 14 74 Timing chart of up counting mode change TIMERx_CAR on the go TIMER_CK CEN PSC_CLK CNT_REG 94 95 96 97 98 99 0 1 2 3 4 5 6 7 Update event UPE Update interrupt flag UPIF Auto reload register 120 99 change CAR Vaule CNT_REG 113 114 115 116 117 118 119 120 0 1 2 98 99 0 Update event UPE Update interrupt flag UPIF Auto reload register 120 99 change CAR Vaule 120 99 ...

Page 391: ...Underflow Overflow TIMERx_CREP 0x0 TIMER_CK 0 1 98 99 0 1 UPIF TIMERx_CREP 0x1 98 99 0 1 98 99 0 1 UPIF UPIF TIMERx_CREP 0x2 PSC_CLK Input capture and output compare channels The general level4 timer has one independent channels which can be used as capture inputs or compare match outputs Each channel is built around a channel capture compare register including an input stage channel controller an...

Page 392: ...annel and trig controlled by CHxMS The IC_prescaler make several the input event generate one effective capture event On the capture event CHxVAL will restore the value of Counter So the process can be divided to several steps as below Step1 Filter configuration CHxCAPFLT in TIMERx_CHCTL0 Based on the input signal and requested signal quality configure compatible CHxCAPFLT Step2 Edge selection CHx...

Page 393: ... show the principle circuit of channels output compare function The relationship between the channel output signal CHx_O CHx_ON and the OxCPRE signal more details refer to Channel output prepare signal is described as blew The active level of O0CPRE is high the output level of CH0_O CH0_ON depends on OxCPRE signal CHxP CHxNP bit and CH0E CH0NE bit please refer to the TIMERx_CHCTL2 register for mor...

Page 394: ...he shadow enable mode by CHxCOMSEN Set the output mode Set Clear Toggle by CHxCOMCTL Select the active high polarity by CHxP CHxNP Enable the output by CHxEN Step3 Interrupt DMA request enables configuration by CHxIE CHxDEN Step4 Compare output timing configuration by TIMERx_CAR and TIMERx_CHxCV About the CHxVAL you can change it ongoing to meet the waveform you expected Step5 Start the counter by...

Page 395: ...rrupt signal CHxIF CHxOF Channel output prepare signal When the TIMERx is used in the compare match output mode the OxCPRE signal Channel x Output prepare signal is defined by setting the CHxCOMCTL filed The OxCPRE signal has several types of output function These include keeping the original level by setting the CHxCOMCTL field to 0x00 set to 1 by setting the CHxCOMCTL field to 0x01 set to 0 by s...

Page 396: ...and the POEN ROS IOS ISOx and ISOxN bits in the TIMERx_CCHP and TIMERx_CTL1 registers The outputs polarity is determined by CHxP and CHxNP bits in the TIMERx_CHCTL2 register Table 14 7 Complementary outputs controlled by parameters Complementary Parameters Output Status POEN ROS IOS CHxEN CHxNEN CHx_O CHx_ON 0 0 1 0 0 0 CHx_O CHx_ON LOW CHx_O CHx_ON output disable 1 CHx_O CHxP CHx_ON CHxNP CHx_O C...

Page 397: ...tion ensures that no two complementary signals drive the active state at the same time When the channel x match TIMERx counter CHxVAL occurs OxCPRE will be toggled because under PWM0 mode At point A in the Figure 14 80 Complementary output with dead time insertion CHx_O signal remains at the low value until the end of the deadtime delay while CHx_ON will be cleared at once Similarly At point B whe...

Page 398: ...function enabled by setting the BRKEN bit in the TIMERx_CCHP register The break input polarity is setting by the BRKP bit in TIMERx_CCHP When a break occurs the POEN bit is cleared asynchronously the output CHx_O and CHx_ON are driven with the level programmed in the ISOx bit and ISOxN in the TIMERx_CTL1 register as soon as POEN is 0 If IOS is 0 then the timer releases the enable output else the e...

Page 399: ...e CEN bit at a high state until the update event occurs or the CEN bit is written to 0 by software If the CEN bit is cleared to 0 using software the counter will be stopped and its value held In the single pulse mode the trigger active edge which sets the CEN bit to 1 will enable the counter However there exist several clock delays to perform the comparison result between the counter value and the...

Page 400: ...Rx_DMATB In fact register TIMERx_DMATB is only a buffer timer will map the TIMERx_DMATB to an internal register appointed by the field of DMATA in TIMERx_DMACFG If the field of DMATC in TIMERx_DMACFG is 0 1 transfer then the timer s DMA request is finished While if TIMERx_DMATC is not 0 such as 3 4 transfers then timer will send 3 more requests to DMA and DMA will access timer s registers DMATA 0x...

Page 401: ...re to specify division factor between the CK_TIMER and the dead time and digital filter sample clock DTS 00 fDTS fCK_TIMER 01 fDTS fCK_TIMER 2 10 fDTS fCK_TIMER 4 11 Reserved 7 ARSE Auto reload shadow enable 0 The shadow register for TIMERx_CAR register is disabled 1 The shadow register for TIMERx_CAR register is enabled 6 4 Reserved Must be kept at reset value 3 SPM Single pulse mode 0 Single pul...

Page 402: ...ot generate an update event but the counter and prescaler are initialized 0 CEN Counter enable 0 Counter disable 1 Counter enable The CEN bit must be set by software when timer works in external clock pause mode and encoder mode Control register 1 TIMERx_CTL1 Address offset 0x04 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ...

Page 403: ...t 1 The shadow registers update by when CMTG bit is set or a rising edge of TRGI occurs When a channel does not have a complementary output this bit has no effect 1 Reserved Must be kept at reset value 0 CCSE Commutation control shadow enable 0 The shadow registers for CHxEN CHxNEN and CHxCOMCTL bits are disabled 1 The shadow registers for CHxEN CHxNEN and CHxCOMCTL bits are enabled After these bi...

Page 404: ...pdate interrupt enable 0 disabled 1 enabled Interrupt flag register TIMERx_INTF Address offset 0x10 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CH0OF Reserved BRKIF Reserved CMTIF Reserved CH0IF UPIF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31 10 Reserve...

Page 405: ...rupt occurred 4 2 Reserved Must be kept at reset value 1 CH0IF Channel 0 s capture compare interrupt flag This flag is set by hardware and cleared by software When channel 0 is in input mode this flag is set when a capture event occurs When channel 0 is in output mode this flag is set when a compare event occurs 0 No Channel 0 interrupt occurred 1 Channel 0 interrupt occurred 0 UPIF Update interru...

Page 406: ...are event generation This bit is set by software in order to generate a capture or compare event in channel 0 it is automatically cleared by hardware When this bit is set the CH0IF flag is set the corresponding interrupt or DMA request is sent if enabled In addition if channel 1 is configured in input mode the current value of the counter is captured in TIMERx_CH0CV register and the CH0OF flag is ...

Page 407: ...ls to the output compare register TIMERx_CH0CV 100 Force low O0CPRE is forced to low level 101 Force high O0CPRE is forced to high level 110 PWM mode0 When counting up O0CPRE is high when the counter is smaller than TIMERx_CH0CV and low otherwise When counting down O0CPRE is low when the counter is larger than TIMERx_CH0CV and high otherwise 111 PWM mode1 When counting up O0CPRE is low when the co...

Page 408: ...e only when the channel is not active CH0EN bit in TIMERx_CHCTL2 register is reset 00 Channel 0 is programmed as output 01 Channel 0 is programmed as input IS0 is connected to CI0FE0 10 Reserved 11 Reserved Input capture mode Bits Fields Descriptions 31 8 Reserved Must be kept at reset value 7 4 CH0CAPFLT 3 0 Channel 0 input capture filter control The CI0 input signal can be filtered by digital fi...

Page 409: ...00 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CH0NP CH0NEN CH0P CH0EN rw rw rw rw Bits Fields Descriptions 31 4 Reserved Must be kept at reset value 3 CH0NP Channel 0 complementary output polarity When channel 0 is configured in output mode this bit specifies the complementary output signal...

Page 410: ...rigger operation in slave mode And CIxFE0 will be inverted CH0NP 1 CH0P 0 Reserved CH0NP 1 CH0P 1 CIxFE0 s falling and rising edge are both the active signal for capture or trigger operation in slave mode And CIxFE0 will be not inverted This bit cannot be modified when PROT 1 0 bit filed in TIMERx_CCHP register is 11 or 10 0 CH0EN Channel 0 capture compare function enable When channel 0 is configu...

Page 411: ... is divided by PSC 1 to generate the counter clock The value of this bit filed will be loaded to the corresponding shadow register at every update event Counter auto reload register TIMERx_CAR Address offset 0x2C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CARL 15 0 rw Bits Fi...

Page 412: ...he update rate of the shadow registers is also affected by this bit filed when these shadow registers are enabled Channel 0 capture compare value register TIMERx_CH0CV Address offset 0x34 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH0VAL 15 0 rw Bits Fields Descriptions 31 16...

Page 413: ...t is set to 1 at the next update event The bit can be cleared to 0 by Write 0 to this bit Valid fault input asynchronous When one of channels is configured in output mode setting this bit enables the channel outputs CHx_O and CHx_ON if the corresponding enable bits CHxEN CHxNEN in TIMERx_CHCTL2 register have been set 0 Disable channel outputs CHxO or CHxON 1 Enabled channel outputs CHxO or CHxON N...

Page 414: ...re enabled with relationship to CHxEN CHxNEN bits in TIMERx_CHCTL2 register This bit cannot be modified when PROT 1 0 bit filed in TIMERx_CCHP register is 10 or 11 9 8 PROT 1 0 Complementary register protect control This bit filed specifies the write protection property of registers 00 protect disable No write protection 01 PROT mode 0 The ISOx ISOxN bits in TIMERx_CTL1 register and the BRKEN BRKP...

Page 415: ... Reserved Must be kept at reset value 12 8 DMATC 4 0 DMA transfer count This filed defines the number n of the register that DMA will access R W n DMATC 4 0 1 DMATC 4 0 is from 5 b0_0000 to 5 b1_0001 7 5 Reserved Must be kept at reset value 4 0 DMATA 4 0 DMA transfer access start address This filed define the first address for the DMA access the TIMERx_DMATB When access is done through the TIMERx_...

Page 416: ...er TIMERx_CFG Address offset 0xFC Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CHVSEL OUTSEL rw rw Bits Fields Descriptions 31 2 Reserved Must be kept at reset value 1 CHVSEL Write CHxVAL register selection This bit field set and reset by software 1 If write the CHxVAL...

Page 417: ...or DMA request on update event 14 6 3 Block diagram Figure 14 83 Basic timer block diagram provides details on the internal configuration of the basic timer Figure 14 83 Basic timer block diagram PSC Trigger processor Trigger Selector Counter Counter Register Interrupt Register set and update Interrupt collector APB BUS CK_TIMER CAR TIMERx_TRGO Interrupt Update UPIE TIMER_CK PSC_CLK 14 6 4 Functio...

Page 418: ...PSC_CLK TIMER_CK CNT_REG Reload Pulse 17 18 19 20 21 22 update event generate UPG 23 00 01 02 03 04 05 06 07 Update event UPE Clock prescaler The counter clock PSC_CK is obtained by the TIMER_CK through the prescaler and the prescale factor can be configured from 1 to 65536 through the prescaler register TIMERx_PSC The new written prescaler value will not take effect until the next update event ...

Page 419: ...r will start counting up from 0 again The update event is generated at each counter overflow The counting direction bit DIR in the TIMERx_CTL1 register should be set to 0 for the up counting mode When the update event is set by the UPG bit in the TIMERx_SWEVG register the counter value will be initialized to 0 and generates an update event If the UPDIS bit in TIMERx_CTL0 register is set the update...

Page 420: ... 8 PSC_CLK 97 98 99 0 1 Figure 14 87 Timing chart of up counting mode change TIMERx_CAR on the go TIMER_CK CEN PSC_CLK CNT_REG 94 95 96 97 98 99 0 1 2 3 4 5 6 7 Update event UPE Update interrupt flag UPIF Auto reload register 120 99 change CAR Vaule CNT_REG 113 114 115 116 117 118 119 120 0 1 2 98 99 0 Update event UPE Update interrupt flag UPIF Auto reload register 120 99 change CAR Vaule 120 99 ...

Page 421: ...he single pulse mode it is necessary to set the timer enable bit CEN in the TIMERx_CTL0 register to 1 to enable the counter then the CEN bit keeps at a high state until the update event occurs or the CEN bit is written to 0 by software If the CEN bit is cleared to 0 using software the counter will be stopped and its value held Timer debug mode When the Cortex M23 halted and the TIMERx_HOLD configu...

Page 422: ...alue 3 SPM Single pulse mode 0 Single pulse mode disable The counter continues after update event 1 Single pulse mode enable The counter counts until the next update event occurs 2 UPS Update source This bit is used to select the update event sources by software 0 These events generate update interrupts or DMA requests The UPG bit is set The counter generates an overflow or underflow event The res...

Page 423: ...ts Fields Descriptions 31 7 Reserved Must be kept at reset value 6 4 MMC 2 0 Master mode control These bits control the selection of TRGO signal which is sent in master mode to slave timers for synchronization function 000 When a counter reset event occurs a TGRO trigger signal is output The counter resert source Master timer generate a reset The UPG bit in the TIMERx_SWEVG register is set 001 Ena...

Page 424: ...ate interrupt enable 0 disabled 1 enabled Interrupt flag register TIMERx_INTF Address offset 0x10 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved UPIF rc_w0 Bits Fields Descriptions 31 1 Reserved Must be kept at reset value 0 UPIF Update interrupt flag This bit is set by ...

Page 425: ... No generate an update event 1 Generate an update event Counter register TIMERx_CNT Address offset 0x24 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CNT 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 CNT 15 0 This bit filed indicates the curren...

Page 426: ...it filed will be loaded to the corresponding shadow register at every update event Counter auto reload register TIMERx_CAR Address offset 0x2C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CARL 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 CARL...

Page 427: ...nal The IFRP output PB9 can provide high current to control LED interface by setting PB9_HCCE in SYSCFG_CFG0 15 3 Function overview IFRP is a module which is able to integrate the output of TIMER15 and TIMER16 to generate an infrared ray signal 1 The TIMER15 s CH0 is programed to generate the low frequence PWM signal which is the modulation evalope signal The TIMER16 s CH0 is programed to generate...

Page 428: ...H0 IFRP_OUT TIMER15_CH0 Note Carrier TIMER15_CH0 s duty cycle can be changed and IFRP_OUT has inverted relationship with TIMER16_CH0 when TIMER15_CH0 is high Figure 15 3 IFRP output timechart 3 TIMER16_CH0 IFRP_OUT TIMER15_CH0 Note IFRP_OUT will keep the integrity of TIMER16_CH0 even if evelope signal TIMER15_CH0 is no active ...

Page 429: ...iprocessor communication mode and hardware flow control protocol CTS RTS The data frame can be transferred from LSB or MSB bit The polarity of the TX RX pins can be configured independently and flexibly All USARTs support DMA function for high speed data communication 16 2 Characteristics NRZ standard format Asynchronous full duplex communication Half duplex single wire communication Receive FIFO ...

Page 430: ... buffer not empty RBNE receive FIFO full RFF transmit buffer empty TBE transfer complete TC Flags for error detection overrun error ORERR noise error NERR frame error FERR and parity error PERR Flag for hardware flow control CTS changes CTSF Flag for LIN mode LIN break detected LBDF Flag for multiprocessor communication IDLE frame detected IDLEF Flag for ModBus communication Address character matc...

Page 431: ...gister Receive Shift Register USART Control Registers CK Transimit Controler Hardware Flow Controler nRTS nCTS Receiver Controler USART Address Wakeup Unit USART Guard Time and Prescaler Register USART Status Register USART Interrupt Controler USARTDIV 8 2 OVSMOD USART Baud Rate Register UCLK Transmitter clock Receiver clock Write Buffer Read Buffer Read FiFO 16 3 1 USART frame format The USART fr...

Page 432: ...ollowed by the configured number of stop bits The transfer speed of a USART frame depends on the frequency of the UCLK the configuration of the baud rate generator and the oversampling mode 16 3 2 Baud rate generation The baud rate divider is a 16 bit number which consists of a 12 bit integer and a 4 bit fractional part The number formed by these two values is used by the baud rate generator to de...

Page 433: ...ritten to the USART_TDATA register while a transmission is ongoing it will be firstly stored in the transmit buffer and transferred to the transmit shift register after the current transmission is done If a data is written to the USART_TDATA register while no transmission is ongoing the TBE bit will be cleared and set soon because the data will be transferred to the transmit shift register immedia...

Page 434: ... USART_CTL0 After being enabled the receiver receives a bit stream after a valid start pulse has been detected Detection on noisy error parity error frame error and overrun error is performed during the reception of a frame When a frame is received the RBNE bit in USART_STAT is asserted an interrupt is generated if the corresponding interrupt enable bit RBNEIE is set in the USART_CTL0 register The...

Page 435: ...terrupt is generated If the receive DMA is enabled and the ERRIE bit in USART_CTL2 register is set When a frame is received if the RBNE bit is not cleared yet the last frame will not be stored in the receive data buffer The overrun error ORERR bit in USART_STAT register will be set An interrupt is generated if the receive DMA is enabled and the ERRIE bit in USART_CTL2 register is set or if the RBN...

Page 436: ...in USART_STAT Enable the DMA channel for USART Wait the TC bit to be set After all of the data frames are transmitted the TC bit in USART_STAT is set An interrupt occurs if the TCIE bit in USART_CTL0 is set When DMA is used for USART reception DMA transfers data from the receive data buffer of the USART to the internal SRAM The configuration steps are shown in Figure 16 6 Configuration step when u...

Page 437: ...annel for USART When the number of the data received by USART reaches the DMA transfer number an end of transfer interrupt can be generated in the DMA module 16 3 6 Hardware flow control The hardware flow control function is realized by the nCTS and nRTS pins The RTS flow control is enabled by writing 1 to the RTSEN bit in USART_CTL2 and the CTS flow control is enabled by writing 1 to the CTSEN bi...

Page 438: ...t DEM in the USART_CTL2 control register allows the user to activate the external transceiver control through the DE Driver Enable signal The assertion time which is programmed using the DEA 4 0 bits field in the USART_CTL0 control register is the time between the activation of the DE signal and the beginning of the START bit The de assertion time which is programmed using the DED 4 0 bits field i...

Page 439: ...the receive frame is a 7bit data the LSB 6 bits will be compared with ADDR 5 0 If the ADDM bit is set and the receive frame is a 9bit data the LSB 8 bits will be compared with ADDR 7 0 16 3 8 LIN mode The local interconnection network mode is enabled by setting the LMEN bit in USART_CTL1 The CKEN STB 1 0 bit in USART_CTL1 and the SCEN HDEN IREN bits in USART_CTL2 should be cleared in LIN mode When...

Page 440: ...nt through the CK pin during the transmission of the start bit and stop bit The CLEN bit in USART_CTL1 can be used to determine whether the clock is output or not during the last address flag bit transmission The clock output is also not activated during idle and break frame sending The CPH bit in USART_CTL1 can be used to determine whether data is captured on the first or the second clock edge Th...

Page 441: ...rame is modulated in the SIR transmit encoder and transmitted to the infrared LED through the TX pin The SIR receive decoder receives the modulated signal from the infrared LED through the RX pin and puts the demodulated data frame to the USART receiver The baud rate should not be larger than 115200 for the encoder Figure 16 13 IrDA SIR ENDEC module Normal USART Transmit Encoder Receive Decoder SI...

Page 442: ...tion mode The half duplex communication mode is enabled by setting the HDEN bit in USART_CTL2 The LMEN CKEN bits in USART_CTL1 and SCEN IREN bits in USART_CTL2 should be cleared in half duplex communication mode Only one wire is used in half duplex mode The TX and RX pins are connected together internally The TX pin should be configured as IO pin The conflicts should be controlled by the software ...

Page 443: ...e inserted before the start of a resented frame At the end of the last repeated character the TC bit is set immediately without guard time The USART will stop transmitting and assert the frame error status if it still receives the NACK signal after the programmed number of retries The USART will not take the NACK signal as the start bit During USART reception if the parity error is detected in the...

Page 444: ... after the 4th received character The software must read the third byte as block length from the receive buffer In interrupt driven receive mode the length of the block may be checked by software or by programming the BL value However before the start of the block the maximum value of BL 0xFF may be programmed The real value will be programmed after the reception of the third character The total b...

Page 445: ...verrun error when the CPU can t serve the RBNE interrupt immediately Up to 5 frames receive data can be stored in the receive FIFO and receive buffer The RFFINT flag will be set when the receive FIFO is full An interrupt is generated if the RFFIE bit is set Figure 16 16 USART receive FIFO structure Rx shift register Rx Module FIFO 0 FIFO 1 Rx FIFO EN Rx Buffer DMA FIFO 2 FIFO 3 If the software rea...

Page 446: ...uests Interrupt event Event flag Enable Control bit Transmit data register empty TBE TBEIE CTS flag CTSF CTSIE Transmission complete TC TCIE Received data ready to be read RBNE RBNEIE Overrun error detected ORERR Receive FIFO full RFFINT RFFIE Idle line detected IDLEF IDLEIE Parity error flag PERR PERRIE Break detected flag in LIN mode LBDF LBDIE Reception errors Noise flag overrun error framing e...

Page 447: ...7 Figure 16 17 USART interrupt mapping diagram IDLEF IDLEIE RBNE RBNEIE ORERR RBNEIE PERR PERRIE WUF WUIE LBDF LBDIE AMF AMIE RTF RTIE EBF EBIE FERR NERR ORERR ERRIE OR TC TCIE TBE TBEIE CTSF CTSIE USART_INT RFFINT RFFIE DMA ...

Page 448: ...in USART1 26 RTIE Receiver timeout interrupt enable 0 Disable receiver timeout interrupt 1 Enable receiver timeout interrupt This bit is reserved in USART1 25 21 DEA 4 0 Driver enable assertion time These bits are used to define the time between the activation of the DE driver enable signal and the beginning of the start bit It is expressed in sample time units 1 8 or 1 16 bit time which are confi...

Page 449: ... be written when the USART is enabled UEN 1 9 PM Parity mode 0 Even parity 1 Odd parity This bit field cannot be written when the USART is enabled UEN 1 8 PERRIE Parity error interrupt enable 0 Disable parity error interrupt 1 Enable parity error interrupt An interrupt will occur when the PERR bit is set in USART_STAT 7 TBEIE Transmitter register empty interrupt enable 0 Disable transmitter regist...

Page 450: ...t the clock source for the USART must be IRC8M or LXTAL This bit is reserved in USART1 0 UEN USART enable 0 Disable USART prescaler and outputs 1 Enable USART prescaler and outputs 16 4 2 Control register 1 USART_CTL1 Address offset 0x04 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ADDR 7 0 RTEN Reserved MSBF DINV TINV RINV...

Page 451: ...Data bit level inversion 0 Data bit signal values are not inverted 1 Data bit signal values are inverted This bit field cannot be written when the USART is enabled UEN 1 17 TINV TX pin level inversion 0 TX pin signal values are not inverted 1 TX pin signal values are inverted This bit field cannot be written when the USART is enabled UEN 1 16 RINV RX pin level inversion 0 RX pin signal values are ...

Page 452: ... last data bit MSB is not output to the CK pin in synchronous mode 1 The clock pulse of the last data bit MSB is output to the CK pin in synchronous mode This bit field cannot be written when the USART is enabled UEN 1 7 Reserved Must be kept at reset value 6 LBDIE LIN break detection interrupt enable 0 Disable LIN break detection interrupt 1 Enable LIN break detection interrupt An interrupt will ...

Page 453: ...eserved in USART1 21 20 WUM 1 0 Wakeup mode from Deep sleep mode These bits are used to specify the event which activates the WUF wakeup from Deep sleep mode flag in the USART_STAT register 00 WUF active on address match which is defined by ADDR and ADDM 01 Reserved 10 WUF active on Start bit 11 WUF active on RBNE This bit field cannot be written when the USART is enabled UEN 1 This bit is reserve...

Page 454: ...a reception error The DMA request is not asserted until the error flag is cleared The RBNE flag and corresponding error flag will be set The software must first disable the DMA request DMAR 0 or clear RBNE before clearing the error flag This bit field cannot be written when the USART is enabled UEN 1 12 OVRD Overrun disable 0 Enable overrun functionality The ORERR error flag will be set when recei...

Page 455: ...his bit is reserved in USART1 4 NKEN NACK enable in Smartcard mode 0 Disable NACK transmission when parity error 1 Enable NACK transmission when parity error This bit field cannot be written when the USART is enabled UEN 1 This bit is reserved in USART1 3 HDEN Half duplex enable 0 Disable Half duplex mode 1 Enable Half duplex mode This bit field cannot be written when the USART is enabled UEN 1 2 ...

Page 456: ...ed Must be kept at reset value 15 4 BRR 15 4 Integer of baud rate divider INTDIV 11 0 BRR 15 4 3 0 BRR 3 0 Fraction of baud rate divider If OVSMOD 0 FRADIV 3 0 BRR 3 0 If OVSMOD 1 FRADIV 3 1 BRR 2 0 BRR 3 must be reset 16 4 5 Prescaler and guard time configuration register USART_GP Address offset 0x10 Reset value 0x0000 0000 This register cannot be written when the USART is enabled UEN 1 This regi...

Page 457: ... source clock by 2 00010 divides the source clock by 4 00011 divides the source clock by 6 This bit field cannot be written when the USART is enabled UEN 1 16 4 6 Receiver timeout register USART_RT Address offset 0x14 Reset value 0x0000 0000 This bit is reserved in USART1 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BL 7 0 RT 23 16 rw rw 15 14 13 ...

Page 458: ...ce per received character 16 4 7 Command register USART_CMD Address offset 0x18 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TXFCMD RXFCMD MMCMD SBKCMD Reserved w w w w Bits Fields Descriptions 31 5 Reserved Must be kept at reset value 4 TXFCMD Transmit data flush requ...

Page 459: ...ts the transmit enable state of the USART core logic 0 The USART core transmitting logic has not been enabled 1 The USART core transmitting logic has been enabled 20 WUF Wakeup from Deep sleep mode flag 0 No wakeup from Deep sleep mode 1 Wakeup from Deep sleep mode An interrupt is generated if WUFIE 1 in the USART_CTL2 register and the MCU is in Deep sleep mode This bit is set by hardware when a w...

Page 460: ...nd of Block not reached 1 End of Block number of characters reached An interrupt is generated if the EBIE 1 in the USART_CTL1 register Set by hardware when the number of received bytes from the start of the block including the prologue is equal or greater than BLEN 4 Cleared by writing 1 to EBC bit in USART_INTC register This bit is reserved in USART1 11 RTF Receiver timeout flag 0 Timeout value n...

Page 461: ... bit of the USART_CMD register Cleared by a write to the USART_TDATA 6 TC Transmission completed 0 Transmission is not completed 1 Transmission is complete An interrupt will occur if the TCIE bit is set in USART_CTL0 Set by hardware if the transmission of a frame containing data is completed and if the TBE bit is set Cleared by writing 1 to TCC bit in USART_INTC register 5 RBNE Read data buffer no...

Page 462: ...is detected In multibuffer communication an interrupt will occur if the ERRIE bit is set in USART_CTL2 Set by hardware when a de synchronization excessive noise or a break character is detected This bit will be set when the maximum number of transmit attempts is reached without success the card NACKs the data frame when USART transmits in smartcard mode Cleared by writing 1 to FEC bit in USART_INT...

Page 463: ...1 10 Reserved Must be kept at reset value 9 CTSC CTS change clear Writing 1 to this bit clears the CTSF bit in the USART_STAT register 8 LBDC LIN break detected clear Writing 1 to this bit clears the LBDF flag in the USART_STAT register This bit is reserved in USART1 7 Reserved Must be kept at reset value 6 TCC Transmission complete clear Writing 1 to this bit clears the TC bit in the USART_STAT r...

Page 464: ...ending on the data length will be the received parity bit if receiving with the parity is enabled PCEN bit set to 1 in the USART_CTL0 register 16 4 11 Transmit data register USART_TDATA Address offset 0x28 Reset value 0xXXXX XXXX This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TDATA 8 0 rw Bits ...

Page 465: ...cted which is before RBNE flag This flag is cleared by writing 0 0 No parity error is detected 1 Parity error is detected 7 1 Reserved Must be kept at reset value 0 HCM Hardware flow control coherence mode 0 nRTS signal equals to the RBNE in status register 1 nRTS signal is set when the last data bit parity bit when pce is set has been sampled 16 4 13 USART receive FIFOcontrol and status register ...

Page 466: ...rupt enable 0 Receive FIFO full interrupt disable 1 Receive FIFO full interrupt enable 8 RFEN Receive FIFO enable This bit can be set when UESM 1 0 Receive FIFO disable 1 Receive FIFO enable 7 1 Reserved Must be kept at reset value 0 ELNACK Early NACK when smartcard mode is selected The NACK pulse occurs 1 16 bit time earlier when the parity error is detected 0 Early NACKdisable when smartcard mod...

Page 467: ...2C bus The I2C interface provides DMA mode for users to reduce CPU overload 17 2 Characteristics Parallel bus to I2C bus protocol converter and interface Both master and slave functions with the same interface Bi directional data transfer between master and slave Supports 7 bit and 10 bit addressing and General Call Addressing Multi master capability Supports standard mode up to 100 kHz fast mode ...

Page 468: ...orrupting the message Synchronization Procedure to synchronize the clock signals of two or more devices Arbitration Procedure to ensure that if more than one master tries to control the bus simultaneously only one is allowed to do so and the winning master s message is not corrupted 17 3 1 SDA and SCL lines The I2C module has two external lines the serial data SDA and serial clock SCL lines The tw...

Page 469: ... A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP signal Figure 17 3 START and STOP signal SDA SCL SDA SCL START STOP 17 3 4 Clock synchronization Two masters can begin transmitting on a free bus at the same time and there must be a method for deciding which master takes control of the bus and completes its transmission This is done by clock synchronization and bus arbitra...

Page 470: ... can even complete an entire transmission without error as long as the transmissions are identical The first time a master tries to send a HIGH but detects that the SDA level is LOW then the master knows that it has lost the arbitration and turns off its SDA output driver The other master goes on to complete its transmission Figure 17 5 SDA line arbitration SDA SCL SDA from master2 SDA from master...

Page 471: ...er to slave From slave to master Slave address byte1 header ACK 1 1 1 1 0 x x ACK Slave address byte1 header Start R 1 17 3 7 Programming model An I2C device such as LCD driver may only be a receiver whereas a memory can both receive and transmit data In addition to transmitters and receivers devices can also be considered as masters or slaves when performing data transfers A master is the device ...

Page 472: ...use both the shift register and data register I2C_DATA are empty Once TBE is set software should write the first byte of data to I2C_DATA register TBE is not cleared in this case because the byte written in I2C_DATA is moved to the internal shift register immediately I2C begins to transmit data to I2C bus as soon as the shift register is not empty 4 During the transmission of the first byte softwa...

Page 473: ...te Hardware Action Software Flow Master sends Header Slave sends Acknowledge Programming model in slave receiving mode As is shown in Figure 17 10 Programming model for slave receiving 10 bit address mode the following software procedure should be followed if users wish to receive data in slave receiver mode 1 First of all enable I2C peripheral clock as well as configure clock related registers in...

Page 474: ...e procedure should be followed if users wish to make transaction in master transmitter mode 1 First of all enable I2C peripheral clock as well as configure clock related registers in I2C_CTL1 to make sure correct I2C timing After enabled and configured I2C operates in its default slave state and waits for START signal followed by address on I2C bus 2 Software sets START bit requesting I2C to gener...

Page 475: ...C master sets BTC bit because both the shift register and I2C_DATA are empty Software should set the STOP bit to generate a STOP signal then the I2C clears both TBE and BTC flags Figure 17 11 Programming model for master transmitting 10 bit address mode IDLE Master generates START condition Master sends Address Slave sends Acknowledge Master sends Header Slave sends Acknowledge SCL stretched by ma...

Page 476: ...ould clear the ADD10SEND bit by reading I2C_STAT0 and writing 10 bit lower address to I2C_DATA 4 After the 7 bit or 10 bit address has been sent the I2C hardware sets the ADDSEND bit and software should clear the ADDSEND bit by reading I2C_STAT0 and then I2C_STAT1 If the address is in 10 bit format software should then set START bit again to generate a repeated START signal on I2C bus and SBSEND i...

Page 477: ...ter 6 Read DATA N 1 7 Clear ACKEN Set STOP Solution B 1 First of all enable I2C peripheral clock as well as configure clock related registers in I2C_CTL1 to make sure correct I2C timing After enabled and configured I2C operates in its default slave state and waits for START signal followed by address on I2C bus 2 Software sets START bit requesting I2C to generate a START signal on I2C bus 3 After ...

Page 478: ...is stretched by master to prevent the reception of the last byte Then software should clear ACKEN bit 7 Software reads out N 2 byte clearing BTC After this the N 1 byte is moved from shift register to I2C_DATA and bus is released and begins to receive the last byte Master doesn t send an ACK for the last byte because ACKEN is already cleared 8 After the last byte is received both BTC and RBNE are ...

Page 479: ... master 3 Clear SBSEND SCL stretched by master 4 Set START Master generates repeated START condition Set SBSEND 4 Clear SBSEND SCL stretched by master Master sends Header Slave sends Acknowledge Set ADDSEND 4 Clear ADDSEND SCL stretched by master 7 Clear ACKEN Slave sends DATA N 2 Master sends Acknowledge SCL stretched by master Set RBNE and BTC 8 Read DATA N 1 7 Set STOP SCL stretched by master 9...

Page 480: ...will send an End of Transmission EOT signal to the I2C interface and generates a DMA full transfer finish interrupt When a master receives two or more bytes the DMALST bit in the I2C_CTL1 register should be set The I2C master will send NACK after the last byte The STOP bit can be set by software to generate a STOP signal in the ISR of the DMA full transfer finish interrupt When a master receives o...

Page 481: ...d unique addresses This advantage results in a plug and play user interface In this protocol there is a very useful distinction between a system host and all the other devices in the system that is the host provides address assignment function Time out feature SMBus has a time out feature which resets devices if a communication takes too long This explains the minimum clock frequency is 10 kHz to ...

Page 482: ...ment the function of ARP protocol 3 In order to support SMBus Alert Mode the software should respond to SMBALT flag and implement the related function 17 3 12 SAM_V support To support the SAM_V standard two additional pins are added to the I2C module txframe and rxframe Txframe is an output pin in master mode it indicates the I2C is busy when it is asserted Rxframe is an input pin that is supposed...

Page 483: ...ected RFF SAM_V mode rxframe pin falling edge is detected TFR SAM_V mode txframe pin rising edge is detected TFF SAM_V mode txframe pin falling edge is detected Table 17 3 Error flags Error Name Description BERR Bus error LOSTARB Arbitration lost OUERR Over run or under run when SCL stretch is disabled AERR No acknowledge received PECERR CRC value doesn t match SMBTO Bus timeout in SMBus mode SMBA...

Page 484: ...t until the I2C lines are released to reset the I2C 0 I2C is not under reset 1 I2C is under reset 14 Reserved Must be kept at reset value 13 SALT SMBus Alert Issue alert through SMBA pin Software can set and clear this bit and hardware can clear this bit 0 Don t issue alert through SMBA pin 1 Issue alert through SMBA pin 12 PECTRANS PEC transfer Software sets and clears this bit while hardware cle...

Page 485: ...rate a START signal on I2C bus This bit is set and cleared by software and cleared by hardware when a START signal is detected or I2CEN 0 0 START will not be sent 1 START will be sent 7 SS Whether to stretch SCL low when data is not ready in slave mode This bit is set and cleared by software 0 SCL stretching is enabled 1 SCL stretching is disabled 6 GCEN Whether or not to response to a General Cal...

Page 486: ...xt DMA EOT is the last transfer 11 DMAON DMA mode switch 0 DMA mode switched off 1 DMA mode switched on 10 BUFIE Buffer interrupt enable 0 Buffer interrupt is disabled TBE 1 or RBNE 1 when EVIE 1 will not generate an interrupt 1 Buffer interrupt is enabled which means that interrupt will be generated when TBE 1 or RBNE 1 if EVIE 1 9 EVIE Event interrupt enable 0 Event interrupt is disabled 1 Event...

Page 487: ...n 24MHz 17 4 3 Slave address register 0 I2C_SADDR0 Address offset 0x08 Reset value 0x0000 0000 This register can be accessed by half word 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDFOR MAT Reserved ADDRESS 9 8 ADDRESS 7 1 ADDRES S0 rw rw rw rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 ADDFORMA...

Page 488: ...mode is enabled 17 4 5 Transfer buffer register I2C_DATA Address offset 0x10 Reset value 0x0000 0000 This register can be accessed by half word 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TRB 7 0 rw Bits Fields Descriptions 31 8 Reserved Must be kept at reset value 7 0 TRB 7 0 Transmission or reception data buffer 17...

Page 489: ...ated PEC 1 Received PEC doesn t match the calculated PEC I2C will send NACK careless of ACKEN bit 11 OUERR Over run or under run situation occurs in slave mode when SCL stretching is disabled In slave receiving mode if the last byte in I2C_DATA is not read out while the following byte is already received over run occurs In slave transmitting mode if the current byte is already sent out while the I...

Page 490: ... then writing I2C_CTL0 0 STOP signal not detected in slave mode 1 STOP signal detected in slave mode 3 ADD10SEND Header of 10 bit address is sent in master mode This bit is set by hardware and cleared by reading I2C_STAT0 and writing I2C_DATA 0 No header of 10 bit address is sent in master mode 1 Header of 10 bit address is sent in master mode 2 BTC Byte transmission is completed If a byte is alre...

Page 491: ... 4 3 2 1 0 PECV 7 0 DUMODF HSTSMB DEFSMB RXGC Reserved TR I2CBSY MASTER r r r r r r r r Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 8 PECV 7 0 Packet Error Checking value that calculated by hardware when PEC is enabled 7 DUMODF Dual flag in slave mode indicates which address matches with the address in Dual Address mode This bit is cleared by hardware after a STOP or a S...

Page 492: ...ER A flag indicating whether I2C block is in master or slave mode This bit is set by hardware when a START signal generates This bit is cleared by hardware after a STOP signal or I2CEN 0 or LOSTARB 1 0 Slave mode 1 Master mode 17 4 8 Clock configure register I2C_CKCFG Address offset 0x1C Reset value 0x0000 0000 This register can be accessed by half word 16 bit or word 32 bit 31 30 29 28 27 26 25 2...

Page 493: ...0000 0002 This register can be accessed by half word 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved RISETIME 6 0 rw Bits Fields Descriptions 31 7 Reserved Must be kept at reset value 6 0 RISETIME 6 0 Maximum rise time in master mode The RISETIME value should be the maximum SCL rise time incremented by 1 17 4 10 SAM cont...

Page 494: ... Rxframe fall interrupt disabled 1 Rxframe fall interrupt enabled 5 TFRIE Txframe rise interrupt enable 0 Txframe rise interrupt disabled 1 Txframe rise interrupt enabled 4 TFFIE Txframe fall interrupt enable 0 Txframe fall interrupt disabled 1 Txframe fall interrupt enabled 3 2 Reserved Must be kept at reset value 1 STOEN SAM_V interface timeout detect enable 0 SAM_V interface timeout detect disa...

Page 495: ...nual 495 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FMPEN rw Bits Fields Descriptions 31 1 Reserved Must be kept at reset value 0 FMPEN Fast mode plus enable The I2C device supports up to 1MHz when this bit is set ...

Page 496: ...tion with full duplex or half duplex or simplex mode Separate transmission and reception buffer 16 bits wide only in SPI0 Separate transmission and reception 32 bit FIFO only in SPI1 Data frame size can be 8 or 16 bits only in SPI0 Data frame size can be 4 to 16 bits only in SPI1 Bit order can be LSB or MSB Software and hardware NSS management Hardware CRC calculation transmission and checking Tra...

Page 497: ...ion not Quad SPI mode Table 18 1 SPI signal description Pin name Direction Description SCK I O Master SPI clock output Slave SPI clock input MISO I O Master data reception line Slave data transmission line Master with bidirectional mode not used Slave with bidirectional mode data transmission and reception line MOSI I O Master data transmission line Slave data reception line Master with bidirectio...

Page 498: ...able 18 2 Quad SPI signal description Pin name Direction Description SCK O SPI clock output MOSI I O Transmission Reception data 0 MISO I O Transmission Reception data 1 IO2 I O Transmission Reception data 2 IO3 I O Transmission Reception data 3 NSS O NSS output 18 3 3 SPI clock timing and data format CKPL and CKPH bits in SPI_CTL0 register decide the timing of SPI clock and data signal The CKPL b...

Page 499: ... 4 D1 0 D0 5 D0 1 D1 5 D1 1 sample IO2 IO3 D0 6 D0 2 D1 6 D1 2 D0 7 D0 3 D1 7 D1 3 SCK In SPI1 normal mode the length of data is configured by the DZ 3 0 bits in the SPI_CTL1 register It can be set from 4 bit up to 16 bit length and the setting applies for both transmission and reception and the read access to the FIFO must be aligned with the BYTEN bit in the SPI_CTL1 register The data frame leng...

Page 500: ...TBE bit is set writing data to the SPI_DATA register will store the data at the end of the TXFIFO Hardware sets the RBNE bit when the RXFIFO is considered non empty 2 When the RBNE bit is set reading data from the SPI_DATA register will get the oldest data from the RXFIFO Note 1 For SPI1 the TXFIFO empty means that the TXFIFO level is less than or equal to half of its capacity The meaning of TXFIF...

Page 501: ...event will be generated when the two frames of data are received Note when an odd number of data bytes will be transferred on the transmitter side writing the last data frame of any odd sequence with an 8 bit access to SPI_DATA is enough The receiver has to change BYTEN for the last data frame received in the odd sequence of frames in order to generate the RBNE event 18 3 5 NSS function Slave mode...

Page 502: ...S goes low after enabling SPI Master hardware NSS input mode MSTMOD 1 SWNSSEN 0 NSSDRV 0 Applicable to multi master mode At this time NSS is configured as hardware input mode Once the NSS pin is pulled low SPI will automatically enter slave mode and a master configuration error will occur and the CONFERR bit will be set to 1 Master software NSS mode MSTMOD 1 SWNSSEN 1 SWNSS 0 NSSDRV Don t care App...

Page 503: ...DEN 1 BDOEN 0 MOSI reception MISO not used SFD Slave full duplex MSTMOD 0 RO 0 BDEN 0 BDOEN Don t care MOSI reception MISO transmission STU Slave transmission with unidirectional connection MSTMOD 0 RO 0 BDEN 0 BDOEN Don t care MOSI not used MISO transmission SRU Slave reception with unidirectional connection MSTMOD 0 RO 1 BDEN 0 BDOEN Don t care MOSI reception MISO not used STB Slave transmission...

Page 504: ...simplex connection Master receive Slave transmit Master MRU MISO MOSI SCK NSS Slave STU MISO MOSI SCK NSS Figure 18 9 A typical simplex connection Master transmit only Slave receive Master MTU MISO MOSI SCK NSS Slave SRU MISO MOSI SCK NSS Figure 18 10 A typical bidirectional connection Master MTB MRB MISO MOSI SCK NSS Slave SRB STB MISO MOSI SCK NSS ...

Page 505: ...its should not be changed SPI1 Before transmitting or receiving data application should follow the SPI initialization sequence described below 1 If master mode or slave TI mode is used program the PSC 2 0 bits in SPI_CTL0 register to generate SCK with desired baud rate or configure the Td time in TI mode otherwise ignore this step 2 Configure the clock timing register CKPL and CKPH bits in the SPI...

Page 506: ...on sequence After the last valid sample clock the incoming data will be moved from shift register to the reception buffer RXFIFO and RBNE will be set The application should read SPI_DATA register to get the received data and this will clear the RBNE flag automatically when reception buffer RXFIFO is empty In MRU and MRB modes hardware continuously sends clock signal to receive the next data frame ...

Page 507: ...3 D 2 D 1 D 0 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 SCK NSS MOSI MISO sample Figure 18 12 Timing diagram of TI master mode with continuous transfer D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 SCK NSS MOSI MISO sample In master TI mode SPI can perform continuous or non continuous transfer I...

Page 508: ...the NSS signal and sets an error flag FERR if it detects an incorrect NSS behavior for example toggles at the middle bit of a byte NSS pulse mode operation sequence This function is controlled by NSSP bit in SPI_CTL1 register In order to implement this function several additional conditions must be met configure the device to master mode frame format should follow the normal SPI protocol select th...

Page 509: ...ration modes in Quad SPI mode quad write and quad read decided by QRD bit in SPI_QCTL register Quad write operation SPI works in quad write mode when QMOD is set and QRD is cleared in SPI_QCTL register In this mode MOSI MISO IO2 and IO3 are all used as output pins SPI begins to generate clock on SCK line and transmit data on MOSI MISO IO2 and IO3 as soon as data is written into SPI_DATA TBE is cle...

Page 510: ...ly to generate SCK clocks so the written data can be any value Once SPI starts transmission it always checks SPIEN and TBE status at the end of a frame and stops when condition is not met So dummy data should always be written into SPI_DATA to generate SCK The operation flow for receiving in quad mode is shown below 1 Configure clock prescaler clock polarity phase etc in SPI_CTL0 and SPI_CTL1 regi...

Page 511: ... 1 0 00 MTU MTB STU STB For SPI0 write the last data into SPI_DATA and wait until the TBE flag is set and then wait until the TRANS flag is cleared Disable the SPI by clearing SPIEN bit For SPI1 wait until TXLVL 1 0 00 and confirm TRANS 0 Then disable the SPI by clearing SPIEN bit MRU MRB For SPI0 after getting the second last RBNE flag read out this data and delay for a SCK clock time and then di...

Page 512: ...t enable SPI After being enabled If DMATEN is set SPI will generate a DMA request each time when TBE 1 then DMA will acknowledge to this request and write data into the SPI_DATA register automatically If DMAREN is set SPI will generate a DMA request each time when RBNE 1 then DMA will acknowledge to this request and read data from the SPI_DATA register automatically Data merging with DMA Only for ...

Page 513: ...C function is invalid CRC data exchange usually requires one or more data communication time after the end of the data sequence For example when setting the data length to 8 bits and doing a 16 bit CRC check it takes two frames to send the complete CRC data If the DMA function is enabled the hardware will handle the CRC transmission and verification automatically but the SPI needs to set the count...

Page 514: ...the CONFERR is set when the SWNSS bit is 0 When the CONFERR is set the SPIEN bit and the MSTMOD bit are cleared by hardware the SPI is disabled and the device is forced into slave mode The SPIEN and MSTMOD bit are write protection until the CONFERR is cleared The CONFERR bit of the slave cannot be set In a multi master configuration the device can be in slave mode with CONFERR bit set which means ...

Page 515: ...I2S_CK I2S_MCK Master Control Logic Slave Control Logic TX Buffer Shift Register RX Buffer Control Registers 16 bits SYSCLK 16 bits LSB MSB PAD PAD O I O I PAD O I PAD O I APB There are five sub modules to support I2S function including control registers clock generator master control logic slave control logic and shift register All the user configuration registers are implemented in the control r...

Page 516: ...er than or equal to the data length four packet types are available They are 16 bit data packed in 16 bit frame 16 bit data packed in 32 bit frame 24 bit data packed in 32 bit frame and 32 bit data packed in 32 bit frame The data buffer for transmission and reception is 16 bit wide In the case that the data length is 24 bits or 32 bits two write or read operations to or from the SPI_DATA register ...

Page 517: ...d operations to or from the SPI_DATA register are needed to complete the transmission of a frame In transmission mode if a 32 bit data is going to be sent the first data written to the SPI_DATA register should be the higher 16 bits and the second one should be the lower 16 bits In reception mode if a 32 bit data is received the first data read from the SPI_DATA register should be higher 16 bits an...

Page 518: ...L 1 I2S_CK I2S_SD 16 bit data frame 1 channel left frame 2 channel right MSB I2S_WS LSB 16 bit 0 MSB When the packet type is 16 bit data packed in 32 bit frame only one write or read operation to or from the SPI_DATA register is needed to complete the transmission of a frame The remaining 16 bits are forced by hardware to 0x0000 to extend the data to 32 bit format MSB justified standard For MSB ju...

Page 519: ...g diagram DTLEN 01 CHLEN 1 CKPL 1 I2S_CK I2S_SD 24 bit data frame 1 channel left frame 2 channel right MSB I2S_WS LSB 8 bit 0 MSB Figure 18 32 MSB justified standard timing diagram DTLEN 00 CHLEN 1 CKPL 0 I2S_CK I2S_SD 16 bit data frame 1 channel left frame 2 channel right MSB I2S_WS LSB 16 bit 0 MSB Figure 18 33 MSB justified standard timing diagram DTLEN 00 CHLEN 1 CKPL 1 I2S_CK I2S_SD 16 bit da...

Page 520: ...tten to the SPI_DATA register should be a 16 bit data The higher 8 bits of the 16 bit data can be any value and the lower 8 bits should be D 23 16 The second data written to the SPI_DATA register should be D 15 0 In reception mode if a 24 bit data D 23 0 is received the first data read from the SPI_DATA register is a 16 bit data The high 8 bits of this 16 bit data are zeros and the lower 8 bits ar...

Page 521: ...short frame synchronization mode are shown below Figure 18 38 PCM standard short frame synchronization mode timing diagram DTLEN 00 CHLEN 0 CKPL 0 I2S_CK I2S_SD 16 bit data MSB I2S_WS MSB LSB frame 1 frame 2 Figure 18 39 PCM standard short frame synchronization mode timing diagram DTLEN 00 CHLEN 0 CKPL 1 I2S_CK I2S_SD 16 bit data MSB I2S_WS MSB LSB frame 1 frame 2 Figure 18 40 PCM standard short f...

Page 522: ...tandard short frame synchronization mode timing diagram DTLEN 00 CHLEN 1 CKPL 0 I2S_CK I2S_SD 16 bit data MSB I2S_WS MSB frame 1 frame 2 16 bit 0 Figure 18 45 PCM standard short frame synchronization mode timing diagram DTLEN 00 CHLEN 1 CKPL 1 I2S_CK I2S_SD 16 bit data MSB I2S_WS MSB frame 1 frame 2 16 bit 0 The timing diagrams for each configuration of the long frame synchronization mode are show...

Page 523: ...frame 1 frame 2 13 bits Figure 18 49 PCM standard long frame synchronization mode timing diagram DTLEN 10 CHLEN 1 CKPL 1 I2S_CK I2S_SD 32 bits MSB I2S_WS MSB LSB frame 1 frame 2 13 bits Figure 18 50 PCM standard long frame synchronization mode timing diagram DTLEN 01 CHLEN 1 CKPL 0 I2S_CK I2S_SD 24 bit data MSB I2S_WS MSB frame 1 frame 2 13 bits 8 bit 0 Figure 18 51 PCM standard long frame synchro...

Page 524: ...clock generator is shown as Figure 18 54 Block diagram of I2S clock generator The I2S interface clocks are configured by the DIV bits the OF bit the MCKOEN bit in the SPI_I2SPSC register and the CHLEN bit in the SPI_I2SCTL register The source clock is the system clock CK_SYS The I2S bitrate can be calculated by the formulas shown in Table 18 7 I2S bitrate calculation formulas Table 18 7 I2S bitrat...

Page 525: ...mode slave transmission mode and slave reception mode The direction of I2S interface signals for each operation mode is shown in the Table 18 9 Direction of I2S interface signals for each operation mode Table 18 9 Direction of I2S interface signals for each operation mode Operation mode I2S_MCK I2S_CK I2S_WS I2S_SD Master transmission Output or NU 1 Output Output Output Master reception Output or ...

Page 526: ...e state Configure the I2SSEL bit to select I2S mode Configure the I2SSTD 1 0 bits and the PCMSMOD bit to select I2S standard Configure the I2SOPMOD 1 0 bits to select I2S operation mode Configure the DTLEN 1 0 bits and the CHLEN bit to select I2S data format Configure the TBEIE bit the RBNEIE bit the ERRIE bit to enable I2S interrupt optional Configure the DMATEN bit and the DMAREN bit to enable I...

Page 527: ...nt when the TBE flag goes high At the beginning the I2SCH flag is low indicating the left channel data should be written to the SPI_DATA register In order to disable I2S it is mandatory to clear the I2SEN bit after the TBE flag is high and the TRANS flag is low I2S master reception sequence The RBNE flag is used to control the reception sequence As is mentioned before the RBNE flag indicates the r...

Page 528: ...aster mode The differences between them are described below In slave mode the slave has to be enabled before the external master starts the communication The transmission sequence begins when the external master sends the clock and when the I2S_WS signal requests the transfer of data The data has to be written to the SPI_DATA register before the master initiates the communication Software should w...

Page 529: ...here are four status flags implemented in the SPI_STAT register including TBE RBNE TRANS and I2SCH The user can use them to fully monitor the state of the I2S bus Transmission buffer empty flag TBE This bit is set when the transmission buffer is empty the software can write the next data to the transmission buffer by writing the SPI_DATA register Reception buffer not empty flag RBNE This bit is se...

Page 530: ...pdated and the newly incoming data is lost Format error FERR In slave I2S mode the I2S monitors the I2S_WS signal and an error flag will be set if I2S_WS toggles at an unexpected position I2S interrupt events and corresponding enabled bits are summed up in the Table 18 10 I2S interrupt Table 18 10 I2S interrupt Interrupt flag Description Clear method Interrupt enable bit TBE Transmission buffer em...

Page 531: ... at reset value 15 BDEN Bidirectional enable 0 2 line unidirectional transmit mode 1 1 line bidirectional transmit mode The data transfers between the MOSI pin of master and the MISO pin of slave 14 BDOEN Bidirectional transmit output enable When BDEN is set this bit determines the direction of transfer 0 Work in receive only mode 1 Work in transmit only mode 13 CRCEN CRC calculation enable 0 Disa...

Page 532: ...n SWNSS bit This bit has no meaning in SPI TI mode 8 SWNSS NSS pin selection in NSS software mode 0 NSS pin is pulled low 1 NSS pin is pulled high This bit has an effect only when the SWNSSEN bit is set This bit has no meaning in SPI TI mode 7 LF LSB first mode 0 Transmit MSB first 1 Transmit LSB first This bit has no meaning in SPI TI mode 6 SPIEN SPI enable 0 Disable SPI peripheral 1 Enable SPI ...

Page 533: ...channel only for SPI1 In data merging mode this bit is set if the total number of data to transmit by DMA is odd It has effect only when DMATEN is set and data merging mode enable data size is less than or equal to 8 bit and write access to SPI_DATA is 16 bit wide This field can be written only when SPI is disabled 0 The total number of data to transmit by DMA is even 1 The total number of data to...

Page 534: ...rrors interrupt enable 0 Disable error interrupt 1 Enable error interrupt An interrupt is generated when the CRCERR bit or the CONFERR bit or the FERR bit or the RXORERR bit or the TXURERR bit is set 4 TMOD SPI TI mode enable 0 Disable SPI TI mode 1 Enable SPI TI mode 3 NSSP SPI NSS pulse mode enable 0 Disable SPI NSS pulse mode 1 Enable SPI NSS pulse mode 2 NSSDRV Drive NSS output 0 Disable maste...

Page 535: ...l 11 Full Note The FIFO level here refers to the current actual storage of the FIFO Here the FIFO is considered full when the FIFO level is greater than 1 2 10 9 RXLVL 1 0 RXFIFO level only for SPI1 00 Empty 01 1 4 full 10 1 2 full 11 Full This field has no meaning when SPI is in receive only mode with CRC function enabled Note The FIFO level here refers to the current actual storage of the FIFO H...

Page 536: ...al to the received CRC data at last 1 The SPI_RCRC value is not equal to the received CRC data at last This bit is set by hardware and is able to be cleared by writing 0 This bit is not used in I2S mode 3 TXURERR Transmission underrun error bit 0 No transmission underrun error occurs 1 Transmission underrun error occurs This bit is set by hardware and cleared by a read operation on the SPI_STAT re...

Page 537: ...ception transmission buffer and reception buffer are 8 bits If the Data frame format is set to 16 bit data the SPI_DATA 15 0 is used for transmission and reception transmission buffer and reception buffer are 16 bit For SPI1 the hardware has two FIFOs including TXFIFO and RXFIFO Write data to SPI_DATA will save the data to TXFIFO and read data from SPI_DATA will get the data from RXFIFO Note In fa...

Page 538: ...value in RCRC 7 0 when the data frame format is set to 16 bit data CRC calculation is based on CRC16 standard and saves the value in RCRC 15 0 For SPI1 CRC function is valid only when the data length is 8 bits or 16 bits And if the CRC length is set to 8 bit and the data size is equal to 8 bit the CRC calculation is based on CRC8 standard and saves the value in RCRC 7 0 In addition to this the cal...

Page 539: ...is the calculation is based on CRC16 standard and saves the value in TCRC 15 0 The hardware computes the CRC value after each transmitted bit when the TRANS is set a read to this register could return an intermediate value The different frame formats LF bit of the SPI_CTL0 will get different CRC values This register is reset when the CRCEN bit in SPI_CTL0 register or the SPIxRST bit in RCU reset r...

Page 540: ...S mode is disabled This bit is not used in SPI mode 6 Reserved Must be kept at reset value 5 4 I2SSTD 1 0 I2S standard selection 00 I2S Phillips standard 01 MSB justified standard 10 LSB justified standard 11 PCM standard These bits should be configured when I2S mode is disabled These bits are not used in SPI mode 3 CKPL Idle state clock polarity 0 The idle state of I2S_CK is low level 1 The idle ...

Page 541: ...MCK output enable 0 Disable I2S_MCK output 1 Enable I2S_MCK output This bit should be configured when I2S mode is disabled This bit is not used in SPI mode 8 OF Odd factor for the prescaler 0 Real divider value is DIV 2 1 Real divider value is DIV 2 1 This bit should be configured when I2S mode is disabled This bit is not used in SPI mode 7 0 DIV 7 0 Dividing factor for the prescaler Real divider ...

Page 542: ... to high in single wire mode This bit is only available in SPI1 1 QRD Quad SPI mode read select 0 SPI is in quad wire write mode 1 SPI is in quad wire read mode This bit can only be configured when the SPI is not busy the TRANS bit is cleared This bit is only available in SPI1 0 QMOD Quad SPI mode enable 0 SPI is in single wire mode 1 SPI is in Quad SPI mode This bit can only be configured when th...

Page 543: ...ow power consumption 600μA at 3 3V per amplifer 19 3 Function overview 19 3 1 Enable OPA There are two OPAs enabled by ENAB pin If ENAB is 0 the OPA disabled The PA6 PB1 PA14 PA13 used as general GPIO function If ENAB pin connect to 1 or floating There is internal weak pull up on ENAB pin the OPA enabled The PA6 PB1 PA14 PA13 need to configure to analog or input floating mode 19 3 2 Combinatorial ...

Page 544: ... as set this bit to 1 Writing 0 has no effect on the bit value read clear by read rc_r Software can read this bit Reading this bit automatically clears it to 0 Writing 0 has no effect on the bit value 20 2 List of terms Table 20 2 List of terms Glossary Descriptions Word Data of 32 bit length Half word Data of 16 bit length Byte Data of 8 bit length IAP in application programming Writing 0 has no ...

Page 545: ...GD32E23x User Manual 545 20 3 Available peripherals For availability of peripherals and their number across all MCU series types refer to the corresponding device data datasheet ...

Page 546: ... the WDGT 5 In chapter 10 4 3 of the ADC module add a description about the delay after the ADC enable Jul 2 2020 1 4 1 Modify the description of the CKEN bit field of Control register 1 USART_CTL1 in the USRT chapter 2 In the VDD domain of PMU chapter add the description of VDDA monitor 3 Update Table 5 1 NVIC exception types in Cortex M23 4 Modified the description of bit 15 of Transfer status r...

Page 547: ...y business industrial personal and or household applications only The Products are not designed intended or authorized for use as components in systems designed or intended for the operation of weapons weapons systems nuclear installations atomic energy control instruments combustion control instruments airplane or spaceship instruments transportation instruments traffic signal instruments life su...

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