GD32E23x User Manual
297
Counter center-aligned counting
In the center-aligned counting mode, the counter counts up from 0 to the counter-reload
value and then counts down to 0 alternatively. The TIMER module generates an overflow
event when the counter counts to the counter-reload value subtract 1 in the up-counting
mode and generates an underflow event when the counter counts to 1 in the down-counting
mode. The counting direction bit DIR in the TIMERx_CTL0 register is read-only and indicates
the counting direction when in the center-aligned mode.
Setting the UPG bit in the TIMERx_SWEVG register will initialize the counter value to 0 and
generate an update event irrespective of whether the counter is counting up or down in the
center-aligned counting mode.
The UPIF bit in the TIMERx_INTF register will be set to 1 either when an underflow event or
an overflow event occurs. While the CHxIF bit is associated with the value of CAM in
TIMERx_CTL0. The details refer to
Figure 14-38. Timing chart of center-aligned
If the UPDIS bit in the TIMERx_CTL0 register is set, the update event is disabled.
When an update event occurs, all the shadow registers (counter autoreload register,
prescaler register) are updated.
Figure 14-38. Timing chart of center-aligned counting mode
shows the example of the
counter behavior
when TIMERx_CAR=
0x99
, TIMERx_PSC=0x0
