GE
D
IRECTION
FQ091019, R
EVISION
2
V
IVID Q
N S
ERVICE
M
ANUAL
5-12
Section 5-3 - Front End Unit
5-3-3-4
FPGA Download
The FPGAs contain no configuration upon power-ON; FGPA Download proceeds as follows:
1.) The actual FPGA contents (bit-streams) are written into DSP memory from the Host.
2.) The DSP configures serial port 0 to aid configuration.
3.) The DSP writes the bit-streams to serial port 0.
4.) The DSP verifies that the FPGAs are configured correctly.
5-3-3-5
PCI Connection
The RFI Board interfaces directly to the PCI bus via the DSP PCI to the local bus bridge.
