Dini Group DN9002K10PCI, User Manual

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H A R D W A R E
DN9002K10PCI User Guide www.dinigroup.com 66
INPUTS
CLK_DIMMB_CK2p AM28
CLK_DIMMB_CK2n AN28
Note that on the netlist, these signals connect to the FPGA twice: once on the DDR2 interface
bank (1.8V), and once on the global clock input bank (2.5V). The 2.5V, clock bank connections
should be used as inputs, and the 1.8V bank signals should be configured as outputs. For input
signals, use the LVDSEXT standard with the DIFF_TERM attribute set to TRUE.
4.6.4 SMA Clock A
FPGA A has a pair of SMA connector connected directly to global clock inputs (AM28, AN28).
The bank connected to these signals is a +2.5V bank. Allowed input standards are LVCMOS25,
SSTL25, LVDS, DIFF_SSTL18.
These connections are DC-coupled, meaning the user must ensure that the levels received on
this input are within the limits of the Virtex-5 device to prevent damage to the part.
This pair of SMA connectors can also be used as outputs, or for non-clock signals.
5 Test points
This section lists all of the test points on the DN9002K10PCI. A more detailed description may
be found in the section about the system that the test point is part of, but all test points are listed
here for reference.
J2
CONN_SMA
LIGHTHORSE_SASF546-P26-X1
2
3 4
5
1
CLK_SMA_An
J1
CONN_SMA
LIGHTHORSE_SASF546-P26-X1
2
3 4
5
1
CLK_SMA_Ap