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Dini Group DN9002K10PCI, User Manual

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Dini Group DN9002K10PCI User Manual Download Page 143

H A R D W A R E  

 

Like mating, a connector pair can be unmated by pulling them straight apart. However, it requires less 
effort to un-mate if the force is originated from one of the slot/key ends of the assembly. (Reverse 
procedure from mating) Mating or un-mating of the connector by rolling in a direction perpendicular to 
alignment slots/keys may cause damage to the terminal contacts and is not recommended.

 

 

25.2

 

Daughter Card Electrical 

The daughter card pin out and routing were designed to allow use of the Virtex 5’s 1 Gbps 
general purpose IO. All signals on the DN9002K10PCI are all routed as differential, 50-Ohm 
transmission lines. Signals can be used as single-ended also. Proper electrical levels are explained 
in the VCCO section. 

No length-matching is done on the PCB for daughter card signals, (except between two ends of 
a differential pair), because the Virtex 5 is capable of variable-delay input or output using the 
built-in IDELAY or ODELAY modules. 

25.2.1

 

Pin assignments 

The pin out of the DN9002K10PCI expansion system was designed to reduce cross talk to 
manageable levels while operating at full speed of the Virtex 5. The ground to signal ratio of the 
connector is 1:1. General purpose IO is arranged in a GSGS pattern to allow high speed single-
ended or differential use. On the DN9002K10PCI (host), these signals are routed as loosely-
coupled differential signals, meaning when used differentially, they benefit from the noise-
resistant properties of a differential pair, but when used single-ended-ly, do not interfere with 
each other excessively. 

All high-speed signals on the DN9002K10PCI, including daughter card signals, are routed 
against a ground potential reference plane. When creating a daughter card, it is recommended 
that these signals remain against a ground plane to maintain trace impedance. 

The central columns of the connector pin out use a closely coupled, differential pair pin 
arrangement, which is uniformly surrounded by ground pins. 

Below is a graphic representation of the pin assignments for the 400-pin connectors.  Note that 
this is a view from the backside of the connector. The green boxes represent ground 
connections. 

DN9002K10PCI User Guide 

www.dinigroup.com

 133 

 

Summary of Contents for DN9002K10PCI

Page 1: ...LOGIC Emulation Source UserGuide DN9002K10PCI ...

Page 2: ... DN9002K10PCI User Manual MajorRevision1 LastUpdateFebruary2 2009 The Dini Group 2006 7469 Draper Ave La Jolla CA92037 USA Phone 858 454 3419 Fax 858 454 1728 support dinigroup com www dinigroup com DN9002K10PCI User Guide www dinigroup com ...

Page 3: ......

Page 4: ...tlist 5 3 4 2 Net name conventions 5 3 5 DATASHEET LIBRARY 6 3 6 XILINX 6 3 7 DINI GROUP REFERENCE DESIGNS 6 3 8 BOARD MODELS 6 4 EMAIL AND PHONE SUPPORT 6 CHAPTER 2 QUICK START GUIDE 7 1 PROVIDED MATERIALS 7 1 1 SYSTEM REQUIREMENTS 7 2 WARNINGS 8 2 1 ESD 8 2 2 OTHER 8 2 3 OTHER SPECULATIVE 8 3 PRE POWER ON INSTRUCTIONS 9 3 1 INSTALL MEMORY 10 3 2 PREPARE CONFIGURATION FILES 10 3 3 INSTALL DN9002K...

Page 5: ...2 5 Main Bus 31 1 2 6 Settings Info Menu 32 1 2 7 Production Tests 33 1 2 8 Service Menu 33 1 3 INI FILE 33 2 AETEST USB 34 2 1 COMPILING AETEST_USB 34 2 2 COMPILING THE DRIVER 34 3 PCI AETEST APPLICATION 34 3 1 FUNCTIONALITY 35 3 2 RUNNING AETEST 35 3 3 COMPILING AETEST PCI 37 3 3 1 Compiling AETest for DOS 37 3 3 2 Compiling AETest for Windows XP 38 4 ROLLING YOUR OWN SOFTWARE 38 4 1 USB 38 4 2 ...

Page 6: ... 63 4 4 4 SMA input 63 4 5 PCI CLOCK 64 4 6 NON GLOBAL CLOCKS 64 4 6 1 Clock TP 64 4 6 2 Ethernet Clock 65 4 6 3 DDR2 Clocks 65 4 6 4 SMA Clock A 66 5 TEST POINTS 66 5 1 POWER THRU HOLE 67 5 2 POWER TP 68 5 3 DIMM POWER 68 5 4 GC TEST POINTS 69 5 5 CLOCK TEST POINTS 70 5 6 DIMM SIGNALS 71 6 USB INTERFACE 71 6 1 CONNECTING TO THE DN9002K10PCI 72 6 1 1 Windows XP 72 6 1 2 Windows Vista 72 6 1 3 Linu...

Page 7: ...3 3 PCI Frequency 88 7 4 HOST INTERFACE MECHANICAL 88 7 5 HARDWARE DESIGN NOTES 88 7 6 TROUBLESHOOTING 89 8 UNUSABLE PINS 89 8 1 1 Configuration 89 9 SYSTEM MONITOR ADC 90 10 RESET 90 10 1 POWER RESET 90 10 2 USER RESET 91 11 JTAG 92 11 1 FPGA JTAG 92 11 1 1 Compatible Configuration Devices 93 11 1 2 Identify 93 11 1 3 ChipScope 93 11 2 FIRMWARE UPDATE HEADER 93 11 3 TROUBLESHOOTING 93 12 RS232 IN...

Page 8: ...20 22 6 POWER CONNECTIONS 120 22 7 POWER MONITORS 121 22 8 HEAT 122 22 8 1 Fans 122 22 8 2 Removing Heatsinks 122 22 8 3 Fan Tachometers 122 23 CONNECTORS 123 23 1 FPGA USER INTERFACE CONNECTORS 123 23 1 1 Comments 124 23 2 NON FPGA USER INTERFACE CONNECTORS 124 23 2 1 Comments 125 23 3 NOT FOR USE CONNECTORS 125 23 3 1 Comments 125 24 MECHANICAL 126 25 DAUGHTERCARD HEADERS 127 25 1 DAUGHTER CARD ...

Page 9: ...LES 146 4 2 USING THE DESIGN 146 4 3 RUNNING THE TEST 146 5 CLOCK COUNTERS 147 6 LEDS 147 7 SIMULATING THE REFERENCE DESIGN 147 8 COMPILING THE REFERENCE DESIGN 147 8 1 1 The Xilinx Embedded Development Kit EDK 148 8 1 2 Xilinx XST 148 8 1 3 Xilinx ISE 148 8 1 4 The Build Utility Make bat 148 8 2 BITGEN OPTIONS 148 8 3 VHDL 148 9 LVDS REFERENCE DESIGN 149 9 1 PROVIDED FILES 149 9 2 USING THE DESIG...

Page 10: ...DUCTS 157 4 COMPLIANCE DATA 158 4 1 COMPLIANCE 158 4 1 1 EMI 158 4 1 2 PCI SIG 158 4 2 ENVIRONMENTAL 158 4 2 1 Temperature 158 4 3 EXPORT CONTROL 158 4 3 1 Lead Free 158 4 3 2 The USA Schedule B number based on the HTS 158 4 3 3 Export control classification number ECCN 159 4 4 MISSION CRITICAL 159 ...

Page 11: ...ory modules installed User LEDs power fail LEDs and Gigabit activity LEDs all glowing inexplicably Heatsinks negligently left uninstalled 1 Manual Contents This manual contains the following chapters Introduction Reader s Guide to this manual List of available documentation and resources available Quick Start Guide Step by step instructions for powering on the DN9002K10PCI loading and communicatin...

Page 12: ...al conventions are used in this document Convention Meaning or Use Example Prefix 0x Indicates hexadecimal notation Read from address 0x00110373 returned Letter N Signal is active low INT is active low RSTn is active low 2 2 Manual Content 2 2 1 File names Paths to documents included on the User CD are prefixed with D This refers to your CD drive s root directory when the User CD is inserted in yo...

Page 13: ...ts net names and connections Unmodified Schematics are included in the User CD as a PDF Please refer to this document when designing an interface in the FPGA Use the PDF search feature to search for nets and parts 2 3 Terminology Abbreviations and pronouns are used for some commonly used phrases The user is assumed to know the meaning of the following Spartan Spartan refers to the Spartan 3 FPGA d...

Page 14: ...opment Datasheets A datasheet for every part used on the board You will need these to interface successfully with resources on the DN9002K10PCI Documentation Manual Contains this document FPGA_Reference_Designs Contains the source and compiled program common ming files for the Dini group s DN9002K10 DN9002K10PCI PCI reference design Also board description Programming_Files files and simulation mod...

Page 15: ...lways request a duplicate User CD We will also be happy to provide the latest version of documents via email to customers 3 4 Schematics and Netlist Unmodified Schematics are included in the User CD as a PDF Use the PDF search feature to search for nets and parts 3 4 1 Netlist In lieu of providing a machine readable version of the schematic the Dini Group provides a text netlist of the board This ...

Page 16: ...publications_display jsp 3 7 Dini Group Reference Designs The source code to the reference designs are on the User CD Please copy and use any code you would like The reference designs themselves are not deliverables and as such receive limited support 3 8 Board Models Certify board models and other simulation models for the DN9002K10PCI are provided on the user CD D FPGA_Reference_Designs DN9002K1...

Page 17: ... female DB9 USB cable black CD ROM containing Virtex 5 Reference Designs User manual PDF Board Schematic PDF USB program usbcontroller exe PCI program Aetest exe Source code for USB program PCI program and DN9002K10PCI firmware Board netlist certify model and QL5064 simulation model 1 1 System Requirements To compile Verilog designs for Virtex 5 ISE 9 1 may be required For LX330 designs you may ne...

Page 18: ...uld handle the board using these rails as they are much less ESD sensitive than any other point on the board The 400 pin connectors are not 5V tolerant No exposed surfaces on the board except for the PCI edge connector are tolerant of voltages greater than 4V According to the Virtex 5 datasheets the maximum applied voltage to any IO signals on the FPGA is VCCO This means you should not try to over...

Page 19: ...ronics Do not children play with packaging Do not let children taste wires Do not start smoking It s bad for your health 3 Pre Power on Instructions The image below represents your DN9002K10PCI You will need to know the location of the following parts referenced in this chapter DN9002K10PCI User Guide www dinigroup com 9 ...

Page 20: ...S latency of 3 Almost any modern off the shelf laptop memory The socket DIMMB is connected to FPGA B The socket can accept any capacity DDR2 SODIMM module Note that DDR1 modules will not work in these slots since they are a completely different pin out and voltage level 3 2 Prepare configuration files The DN9002K10PCI reads FPGA configuration data from a CompactFlash card To program the FPGAs on t...

Page 21: ... is wrong and potentially damaging with fire The DN9002K10PCI can also be used in a PCI X slot The rest of this chapter assumes you are installing the board into a Windows XP computer The DN9002K10PCI and provided software is compatible with other operating systems but there is no corresponding quick start guide 3 4 Cables 3 4 1 Connect RS232 Cable The configuration circuit displays status message...

Page 22: ...ot use this voltage this minimum will not be met Under stressful situations the power supply s 5V power rail might become unstable causing the DN9002K10PCI to automatically reset The reference design is not particularly stressful to the power supply and will probably not cause this to occur To work around this limitation you can Use a power supply that does not have a minimum 12V load Attach a dum...

Page 23: ...anity Check on Bit File BIT FILE ATTRIBUTES FILE NAME FPGA_B BIT FILE SIZE 003A943B bytes PART 4vlx100ff151317 05 01 DATA 2005 07 19 TIME 17 05 01 Sanity check passed This line has to do with the firmware update mode The board is setting the global clock frequencies according to the main txt file on the CompactFlash card The messages here are mostly only useful to whoever programmed the firmware P...

Page 24: ...most likely have a problem with the power supply you are connected to and less likely with the DN9002K10PCI 2 Reset LED When the board is in reset for any reason including power failure or pressing the reset button this LED will light RED The LED is located below the RED voltage LEDs next to the logic reset button 3 Check the Spartan FPGA status LED located near pin 1 of the PCI edge connector DS5...

Page 25: ...is location in the search and browse to D USB_Software_Applications driver windows_wdm Select Next In the next window select the item in the list Dini Group ASIC Emulator Click FINISH After Windows installs the driver you will be able to see the following device in the USB Controllers group in the Windows device manager Dini Group ASIC Emulator Update it might be in the ASIC Emulators group 5 2 Op...

Page 26: ...he reference design should already be loaded because you had a CompactFlash card installed when the board powered on let s configure an FPGA over USB Clear an FPGA of its configuration Right click on an FPGA and select from the popup menu Clear FPGA The blue light above the FPGA on the GUI and on the board should turn off To re configure that FPGA using the USB Controller program right click on th...

Page 27: ... via USB please wait File D dn_BitFiles DN9002K10PCI MainTest LX330 fpga_b bit transferred Configured FPGA B via USB Figure 6 USB Controller Log Output The message box below the DN9002K10PCI graphic should display some information about the configuration process When the configuration is successful the green LED should re appear next to the FPGA 5 2 2 Set Clock Frequencies To change the clock freq...

Page 28: ...n this case is prevented from operating it To override this setting hit the Enable USB FPGA communication button near the top of the window To read data from the FPGA design the Dini Group reference design select from the menu MainBus Read In the resulting dialog box enter the address 0x080000000 in the address box and 10 in the number of DWORDs box Press OK and then DONE The result of the read is...

Page 29: ... before continuing this quick start guide Details are in the Software Chapter The rest of this guide assumes you are using Windows XP After you turn your computer on the computer will display a dialog asking for the driver for a Dini Group board with QL5064 PCI Click Choose a driver to install Click Have Disk and browse to D PCI_Software_Applications Aetest wdmdrv drv dndev inf 7 1 1 Use AETest Th...

Page 30: ...can run the PCI test This will write stuff to the PCI reference design that may or may not be loaded into FPGA A and report the results The memory menu is also fun as it lets you display PCI memory space directly and also allows access to the MainBus interface that we used a little earlier DN9002K10PCI User Guide www dinigroup com 20 ...

Page 31: ... test instead It is acceptable to operate the DN9002K10PCI from USB and PCI at the same time The mutual exclusivity of all features is not finalized but it s a safe bet that if you use the MainBus feature from PCI and USB simultaneously the board will do something other than work properly DN9002K10PCI User Guide www dinigroup com 21 ...

Page 32: ... automatically install a driver three times in a row like a retarded parrot The program scans the chain to auto detect the type and number of FPGAs installed on your board and display them on the screen Right click on an FPGA and select choose configuration file Browse to the bit files provided on the user CD D FPGA_Reference_Designs Programming_Files DN9002K10PCI MainTest LX110 fpga _A bit This J...

Page 33: ... learned all of the features that you have to know to start your emulation project If you are new to Xilinx FPGA you might want start by compiling the reference design and adding code to the reference design until you are comfortable with the design flow You should also use the provided UCF constraint file as a starting point for your UCF file 23 ...

Page 34: ......

Page 35: ... to the user FPGA core via USB changing board settings and running hardware tests AETest_usb A cross platform Windows DOS Linux Solaris command line application capable of configuring FPGAs sending data via USB and changing board settings AETest A cross platform Windows XP Windows98 DOS Linux Solaris command line program capable of configuring FPGAs and sending data to and from user FPGA cores via...

Page 36: ... CompactFlash card Clear FPGAs Reset FPGAs Set Global clocks frequency Update firmware for MCU and Spartan The following function interface with the Dini Group reference design Read Write to FPGAs see the chapter Reference Design for a description of the Main bus interface Test DDRs FLASH Reigsters FPGA Interconnect 1 1 Main Window The main USB Controller window has the following components a menu...

Page 37: ...graphic by querying the DN9002K10PCI and reading back its status The USB Controller program does not poll the board and only updates the status when there is some user command Items that may be updated when the refresh button is hit are Type of board connected DN9002K10PCI in this case Number of FPGAs installed DN9002K10PCI User Guide www dinigroup com 27 ...

Page 38: ...ommunication button It can revoke that permission by pressing the Disable USB FPGA communication button When the DN9002K10PCI powers on it begins in the disabled state The state is stored on the board so that multiple programs accessing the DN9002K10PCI may prevent each other from using the Main Bus 1 1 3 Log Window This text box prints the result of each user command in USB Controller There is a ...

Page 39: ...ck on an FPGA in the graphic to show a contextual menu with the options Configure Clear and reconfigure Configure will show an Open dialog for you to select the bit file you wish to use with the FPGA Clear FPGA will clear and reset the FPGA of its current configuration Reconfigure FPGA will configure the FPGA with whatever bit file that this instantiation of USB Controller used to configure that F...

Page 40: ...USB using file this command allows the user to configure more than one FPGA over USB at a time To use this option you must create a setup file that contains information on which FPGA s should be configured and what bitfiles should be used for each FPGA The syntax of this file is similar or identical to the syntax of the CompactFlash main txt interface Details are found in the USB Controller manual...

Page 41: ...enu options without the user having to understand the Main Bus interface or the main bus memory space and it s mapping to the reference design The Main Bus menu allows direct control of the Main Bus This can be useful if you are using your own FPGA core that implements the main bus Write and Read DWORD this displays a dialog box for writing and reading to the Main Bus address space It includes som...

Page 42: ... firmware There are two types of firmware the Flash and the Prom The two types of firmware the reference design and the USB Controller application are only guaranteed to work when using corresponding versions of each If you update one you should update the others 4 Read FPGA temperatures Displays the current temperature of the on die FPGA temperature sensors 5 Force Memory Menu display When the Di...

Page 43: ...e a DDR2 SODIMM installed in each socket before the test is run Headers Test You should uncheck this box It will fail without a test fixture Ethernet Test You should uncheck this box It requires a test fixture External clocks test This test requires a test fixture Test FPGA Q This will test interconnect between FPGA A and FPGA Q LVDS Frequency This is the frequency that the FPGA to FPGA interconne...

Page 44: ...iver Compiling the driver on windows requires the windows driver development kit A script Makeit bat can be run from within the windows DDK build environment Most people don t need to compile the driver in windows because it already works In Linux the driver must be compiled unless you happen to be using the same architecture and OS version as ours when we compiled it 3 PCI AETEST Application AETE...

Page 45: ...PCI devices Various loops for PCI device function and ID numbers Write and Read Configuration DWORD Write DWORD Read DWORD and Write Read DWORD Same Address BAR Memory Fill Write and Display Configure Save BARs from to a file 3 2 Running AETEST The following images show a terminal session in Windows XP The initial display of AETest shows the results of its scan of the PCI bus If the driver for the...

Page 46: ...C O N T R O L L E R S O F T W A R E DN9002K10PCI User Guide www dinigroup com 36 ...

Page 47: ...S version of AETest requires DJGPP You can find it at http www delorie com djgpp Follow the installation instructions for DJGPP The download comes with a utility to set your environment variables correctly D AETest aetest Contains the source code for AETest Copy this directory to your hard drive Open the file DN9002K10PCI User Guide www dinigroup com 37 ...

Page 48: ...ost software requirements to interface with the DN9002K10PCI over PCI are given in the Hardware chapter 5 Updating the Firmware Dini Group may release firmware bug fixes or added features to the DN9002K10PCI If a firmware update is released you will need to download this new code to the firmware flash of the DN9002K10PCI There are three firmware files that Dini Group may release EEPROM_FLP iic for...

Page 49: ...sing corresponding versions of each 5 1 Obtaining the updates The firmware update files are not posted on the web site In order to obtain them you must request them from support dinigroup com You may be required to perform a firmware update to your board to receive support and some features When updating firmware you should update in the following order 1 USB Controller exe http www dinigroup com ...

Page 50: ...se hit Cancel Choose the menu option File Initialize Chain Impact should detect 2 devices in the JTAG chain XC3S1000 and XC18V04 For each item in the chain Impact will direct you to select a programming file for each For the XC3S1000 Press Bypass Impact will then ask for a programming file to program the XC18V04 device select the Spartan Firmware update file provided by Dini Group This file should...

Page 51: ...ct Program from the popup menu In the options dialog that follows the options Erase before programming should be selected and Verify should be selected Press OK The programming process takes an agonizing 35 seconds over the parallel port or a joyful 5 seconds over USB DN9002K10PCI User Guide www dinigroup com 41 ...

Page 52: ...that we provide you 4 After selecting file there will be debug level dialog Please select debug level 0 5 The process takes about 10 15 minutes please leave the board and USBController alone The process bar is on the bottom of USBController window 6 When the execution is finished power cycle the board 5 2 3 Using AEtest_USB If you do not have a JTAG cable you will need to use the following instruc...

Page 53: ...he board when finish You can also use commend line aeusb_wdm_cmd exe XSVF filename xsvf or aeusb_linux_cmd exe XSVF filename xsvf 5 3 Updating EEPROM firmware not recommend To protect against accidental erasure the EEPROM firmware cannot be updated unless the board is put in firmware update mode during power on Find Switch S2 User Reset on the DN9002K10PCI DN9002K10PCI User Guide www dinigroup com...

Page 54: ... close the file 3 Run USBController Update Flash dialog will appear please select NO because we are doing update EEPROM 4 Go to Service menu select Program EEPROM This Process will take about 1 minute Please hit OK 5 Select file EEPROM_FLP iic When USBController completes the update please power cycle power the board 5 3 2 Using AETest_USB 1 Put the board into Firmware Mode See 5 3 2 Run aeusb_wdm...

Page 55: ...update MCU Flash firmware 5 4 1 Using USBController 1 Put the board into Firmware Mode see 5 3 2 Run USBController exe Flash Update dialog will appear please select Yes 3 Please select firmware hex we provide you this file 4 When finish please recycle power the board or hit Hard Reset S3 on the board to boot from User Mode 5 4 2 Using AETest_USB 1 Put the board into Firmware Mode See 5 3 2 Run aeu...

Page 56: ...l take about 2 minutes When it finishes please hit Hard Reset S3 on the board or recycle power the board so that DN9002k10PCI can boot from User Mode Figure 13 aeusb_wdm window You can also run this on the commend line aeusb_wdm_cmd exe FLASH filename hex aeusb_linux_cmd exe FLASH filename hex 46 ...

Page 57: ...ation platform is optimized for providing the maximum amount of interconnect between the Virtex 5 FPGAs It is the highest density off the shelf development board using the Xilinx Virtex 5 FPGA Below is a block diagram of the DN9002K10PCI DN9002K10PCI User Guide www dinigroup com 47 ...

Page 58: ...le ended or LVDS up to 800Mbs DDR2 SODIMM slot Connects to FPGA B 64 bit data width 200MHz operation DDR2 modules PC2 3200 PC2 4200 4GB maximum density per SODIMM when available aggregate data transfer rate 3 2GB s Nine board level global clock networks G0 G1 G2 MB48 EXT0 EXT1 P75 FBA FBB Three separate programmable synthesizers configurable via CompactFlash USB PCI Global clocks networks distribu...

Page 59: ...e FPGAs All pins of all banks of each FPGA are utilized FPGA to FPGA busses are routed and tested LVDS run at 400MHz but can be used single ended at a reduced speed Example designs utilizing the integrated ISERDES OSERDES with DDR for pin multiplexing are included Two separate 400 pin FCI MEG Array connectors allow for customization with daughter cards Signals to from these cards are routed differ...

Page 60: ...als are not externally length matched FPGA interconnect 6 input lookup tables Larger total density parts in terms of total LUT gates More flexible IO 3 Configuration Section Many functions on the DN9002K10PCI are done by circuitry on the DN9002K10PCI external to the FPGA Collectively these circuits are referred to in this document as the Configuration Section The configuration section takes care o...

Page 61: ...ns the configuration section prints messages to the RS232 terminal header The configuration section processes that can be monitored using this header are Temperature sensor FPGA overheat CompactFlash card reading USB configuration PCI configuration Main Bus reads writes Global clock settings MCU RS232_MCU_TXD TSM 136 01 T DV 1 2 3 4 5 6 7 8 9 10 RS232_FPGA_TXD U23 MAX3388E TSOP24 1 2 4 5 6 3 7 8 9...

Page 62: ...figured This documentation refers to this signal as PROG DONE After the FPGA is configured it is driven high or tri stated by the FPGA INIT Low indicates that the FPGA configuration memory is cleared After configuration this could indicate and error RDWR_B Active low write enable This Documentation refers to this signal as RDWR BUSY This signal is not used by the DN9002K10PCI CS_B SelectMap chip s...

Page 63: ...interfere with your design When using these signals as interconnect the appropriate drive standard is LVCMOS25 The IO voltage is 2 5V SelectMap Readback is possible on the DN9002K10PCI This can be accomplished over PCI or USB The user interface for obtaining this data is not defined If you need this feature contact the Dini Group The JTAG configuration method does not go through the configuration ...

Page 64: ...ing the MEMORY MAPPED command To use the main txt interface create a file called main txt on the root directory of the Compact Flash card Plug the card into the DN9002K10PCI The DN9002K10PCI will execute commands contained within this file when the board powers on when the Hard Reset button is pressed or when instructed to do so by the USB interface vendor request A main txt file contains a list o...

Page 65: ...umber in hexadecimal 8 bits WORDADDR 4 digit 32 bit number in hexadecimal representing a main bus address WORDDATA 4 digit 32 bit number in hexadecimal containing data for a main bus transaction The following table describes the function of each of the available main txt commands Instruction Function comment The configuration circuitry performs no operation and moves to the next command VERBOSE LE...

Page 66: ... access features that do not have a main txt command Example applications include setting clock sources settings the EXT0 or EXT1 clock buffers to zero delay mode or setting the clocks to frequencies lower than 31Mhz CLOCK FREQUENCY clockname number MHz The MCU will adjust the clock synthesizer producing clock clockname to the frequency number Currently only frequency settings from 31Mhz to 700Mhz...

Page 67: ...rmatted with the FAT32 file system In this case the DN9002K10PCI will not be able to recognize files on the card 3 5 Configuration Registers The configuration control on the DN9002K10PCI is controlled by setting configuration registers Basically these are just locations in the memory space of the on board micro controller that controls the board s function A full description of the function of thi...

Page 68: ...G2 frequencies below 31 MHz Single step clocking on G0 G1 G2 clock networks Zero Delay Daughtercard clock network External clock source selection Readback of G0 G1 G2 frequency measurements MainBus error counter 3 6 Firmware A Spartan 3 FPGA and a Cypress micro controller control the configuration circuitry The programming data for the FPGA is stored on a flash device and the code for the micro co...

Page 69: ...a very low voltage swing differential signal you cannot receive these signals without using a differential input buffer Single ended inputs will not work An example Verilog implementation of a differential clock input is given below Wire aclk_ibufds IBUFGDS G0CLK_IBUFG O g0clk_ibufg I GCLK0p IB GCLK0n always g0clk_ibufg begin Registers end Either in the UCF or using a synthesis directive you shoul...

Page 70: ...le source of G0 and G1 clock is either the ICS8442 frequency synthesizer or a step clock The step clock is driven by the configuration circuit and can be toggled over USB or PCI by writing to the correct configuration register 0xDF23 2 0xDF23 1 Before the Synthesizer or step clock drives the network the correct source setting must be made in the GUI or in the main txt file By default the source is...

Page 71: ...ation and division settings are possible on the clock synthesizers described above The synthesizer can only do integer multiplication and power of two division Limited resolution When you use USB Controller to set a global clock frequency on the DN9002K10PCI it automatically selects the closest frequency possible from the following lists G0 synthesized from a 25 0 MHz crystal 3 13 6 25 12 50 25 00...

Page 72: ... duty cycle is not guaranteed Experimentally it is shown to be better than 60 40 at high frequencies 4 3 4 Jitter The jitter performance of the G0 G1 and G2 synthesizers is very good but will be a severe limitation at interface speeds above 400Mhz Use the Virtex 5 PLLs 4 4 Ext Clocks There are two clock networks on the DN9002K10PCI that are designed to provide clocks from an external frequency ref...

Page 73: ...ed from the daughtercard B 4 4 3 Daughtercard zero delay mode EXT0 and EXT1 can be set to zero delay mode where each FPGA is able to receive the clock synchronous to the daughtercard This feature requires configuring the clock distribution network with the frequency of the clock The interface by which the user can do this is not defined Contact support dinigroup com if you require this feature Bef...

Page 74: ...on FPGA A or B use a LVCMOS33 input Although the clock is designed to be used with the QL5064_interface_module module it can be used by the user design as well Details about how to connect this clock to the QL5064 module are in the QL5064 module documentation on the user CD Before providing this clock signal to the module you must pass the signal through a DCM and pass the CLK0 output of the DCM t...

Page 75: ...t can be connected to K15 Using this configuration output flip flops connected to CLK0 of the DCM will have an effective clock to out time of less than zero The test point is connected to FPGA A and B on a 3 3V bank This limits the type of signaling that these test points can input or output 4 6 2 Ethernet Clock The VSC8601 Ethernet PHY device outputs a 125Mhz clock The signals in the schematic ar...

Page 76: ...lock inputs AM28 AN28 The bank connected to these signals is a 2 5V bank Allowed input standards are LVCMOS25 SSTL25 LVDS DIFF_SSTL18 These connections are DC coupled meaning the user must ensure that the levels received on this input are within the limits of the Virtex 5 device to prevent damage to the part This pair of SMA connectors can also be used as outputs or for non clock signals 5 Test po...

Page 77: ...for supplying at least 2A regardless of the power requirements or capabilities of the power net 1 0V_A TP16 DNI Pin one is a square Pin two is circular TP14 0 9V_B TP16 1 0V_A TP18 1 0V_B TP23 12V TP10 1 8V TP9 2 5V TP22 1 2V TP15 3 3V TP7 5 0V Power for the 12V 5 0V and 3 3V nets are generated off board These test points are suitable for wiring to if power is needed off board for some reason Or m...

Page 78: ...is a label indicating which power net the test point is connected to These test points are connected by thin traces that are not capable of conducting more than 100mA of current You should only use these test points for probing For noise measurements it is better to use the test points next to each power supply 5 3 DIMM Power As described in the DDR2 Interface section provisions have been made for...

Page 79: ...IMM power to 2 5V If you require 3 3V on this power net no jumper point is provided and you will have to run a wire 5 4 GC Test points Each FPGA is connected to a two pin test point for debugging purposes This test point is the same as the ones used for the Power Thru hole test points Each test point is connected to a GC pin on the FPGA meaning it can be used as a differential clock input to the F...

Page 80: ...test points as two separate IOs this resistor would have to be removed The reference design uses this connection for external clock feedback The register is calleed TPP 5 5 Clock Test points Each of the Global clock networks has a test point These points are not length matched with the global clock network so there may be some phase offset between this point and the FPGA input DN9002K10PCI User Gu...

Page 81: ...he test points are not labeled with their reference designators Instead they are labeled with the signal name 6 USB interface The DN9002K10PCI allows the user FPGA to communicate to a host PC over USB The configuration circuitry allows this by bridging USB to the Main Bus interface For most users implementing USB communication will be as simple as making a Main Bus controller In the reference desi...

Page 82: ... and ProductID 0x1234 The HANDLE object returned by CreateFile is suitable for use with DeviceIoControl 6 1 2 Windows Vista Testing was not complete at print time support dinigroup com 6 1 3 Linux To use USB in Linux use the provided usbdrvlinux c file provided on the user CD in AETest_usb driver Connecting to the device occurs using the driver s usb_open function int handle usb_open 0x1234 0x1234...

Page 83: ... containing the configuration stream for that FPGA VR_END_CONFIG 0xBD This vendor request de selects an FPGA after configuration and returns the configuration status of that FPGA DONE signal VR_MEM_MAPPED Config Read Config Write 0xBE This vendor request reads or writes to the address space of the MCU This vendor request can be used with the configuration register map above to accomplish any confi...

Page 84: ...sters Some of the controls on the DN9002K10PCI do not have their own Vendor Request These functions include setting the clock frequencies In order to accomplish these tasks you must use the Configuration Registers The full list of registers is in the Configuration Section section To write to a configuration register use the VR_MEMORY_MAPPED vendor request The direction is OUT The value field is th...

Page 85: ...ad to EP6 endpoint 6 with the USB bulk request SIZE field set to the number of bytes requested The number requested must be divisible by 4 After the bulk read is complete the address register is incremented by SIZE 4 Read and write transactions use the same Before starting a USB read using a bulk transfer you must tell the DN9002K10PCI how many bytes are going to be read by using the VR_SET_EP6TC ...

Page 86: ... pulsed once for each byte of data sent Note that the LSBit in the USB transaction is sent to the LSBit in the SelectMap interface so bit swapping as described in the Virtex 5 Configuration Guide is not required A standard bit file from Xilinx bitgen can be transferred in binary over this USB interface to correctly configure an FPGA on the DN9002K10PCI Make sure CCLK is selected as the startup clo...

Page 87: ...In response to most vendor requests the MCU will modify or read values in the Configuration memory space see next section Since vendor requests can contain only a limited amount of data USB Bulk transfers are used to send configuration data to the DN9002K10PCI The MCU is too slow to process USB 2 0 data at full speed and so the bulk transfer data is sent to external pins on the Cypress MCU see Cyp...

Page 88: ...his project can be compiled using Xilinx ISE version 7 1i SP4 or later Your board may have been build using an LX80 FF1148 or an LX40 FF1148 for the configuration FPGA 6 5 4 Power The DN9002K10PCI does not draw any power from the USB connector Hot plugging the DN9002K10PCI is acceptable 6 6 Troubleshooting If you cannot get USB to communicate with your design over Main Bus please try using the USB...

Page 89: ...rned 0xABCDABCD This error code is returned when a MainBus register corresponding to a memory is read but the memory is not implemented in the Reference Design 7 PCI interface The DN9002K10PCI can be installed in a PCI slot either 32 or 64 bits 33 or 66Mhz It can also be used in a PCI X slot Although the entire bus will only run at 66Mhz in this configuration A QuickLogic QL5064 bridge provides PC...

Page 90: ...tocol controller does not need to take any of the user space in the FPGA however the Dini Group provides an interface module that should be used in FPGA A This module takes care of IO and clocking concerns and arbitration of some signals on the QL5064 that are shared with the configuration circuitry 7 1 FPGA Interface The FPGA is required to use the supplied QL5064_Interface_module provided on the...

Page 91: ... chaining i e scatter gather for DMA channel 0 only The inputs clock and pci_clock should be generated by a DCM BUFG configuration i e the required BUFG is not instantiated inside the module Pci_clock should be connected to the PCLK_A signal FPGA input Clock may be generated from any FPGA clock input CLK_G0A G1 or even PCLK_A Connect all QL_ signals directly from the DN9002K10PCI User Guide www di...

Page 92: ... same address and byte count as your DMA core so that the data is passed through both FIFOs seamlessly For example if you want to write a block of data to the PCI bus you would do the following Write PCI address to QL5064 register 0x00 T0 address Write source address to your DMA core Write byte count to QL5064 register 0x08 T0 transfer count Write byte count to your DMA core Write a 1 to QL5064 re...

Page 93: ...e This setup allows most systems for meet the memory requirements 7 2 1 Driver The source code for the DN9002K10PCI s PCI driver is provided Windows XP Binaries for 32 bit windows 64 bit windows Intel and 64 bit windows AMD are provided as a binary Use the windows hardware manager to install these drivers Source is provided but shouldn t be required Legacy Windows Versions of Windows older than XP...

Page 94: ...ry map in the Configuration Section and find the entries for G0 M multiply and G0 N divide values Step 3 Write to the G0 M register the value 0x14 20 Write to BAR0 offset 0x258 0xDF300014 Step 4 Write to the G0 N register the value 0x01 2 Write to BAR0 offset 0x258 0xDF290001 Step 5 Write to the UPDATE_FLAG register the value 0x01 CLK G0 Write to BAR0 offset 0x258 0xDF400001 7 2 3 Main Bus The Mai...

Page 95: ...hich FPGA should be selected The data 0x11 represents FPGA A 0x12 is FPGA B Reset the selected FPGA A full chip reset is recommended before configuring an FPGA To reset an FPGA the configuration circuit asserts the FPGA PROGn signal This process clears a device of any configuration it may have Read the current initialization state of the selected FPGA If it is ready to configure it asserts the INT...

Page 96: ... Performance has been characterized using the DN9002K10PCI reference design on Windows XP on a MSI MS6728 motherboard using the AETest application The speeds are Read DN9002K10PCI to software 700Mbs Write software to DN9002K10PCI 350Mbs 7 2 6 Direct PCI to FPGA A Target access If DMA is not required accessing FPGA A from the host software is easy Simply read or write to an address in BAR 1 2 3 4 o...

Page 97: ...compiled from the source code to support your system using an appropriate build environment 7 3 Host Interface Electrical The DN9002K10PCI is compatible with 32 or 64 bit PCI slots It can operate at 33 or 66Mhz at 3 3V or 5 0V You can also install into a PCI X slot and the PCI X bus will automatically revert to a 66 MHz 64 bit PCI bus Be careful not to install the DN9002K10PCI backwards in a PCI s...

Page 98: ...sically fit into a 32 bit PCI connector however there may be components on the motherboard that prevent the board from plugging it Typically there is at least one slot on a generic motherboard that will accommodate the DN9002k10PCI 7 5 Hardware Design Notes The interface between the FPGA and the QL5064 PCI bridge is described briefly in the D FPGA_Reference_Designs DN9002K10PCI PCI_interface QL506...

Page 99: ...cesses the QL5064 on the DN9002K10PCI and writes to registers in the device to tell it what its assigned address ranges are If these registers are not set the QL5064 will not know which bus transactions it should respond to and the bus will return 0xFFFFFFFF on an error One situation that can cause the QL5064 is if the user fails to respond to one or more accesses to an unused BAR If you do not wi...

Page 100: ...This could be used for something I guess 10Reset There are two reset circuits on the DN9002K10PCI One is the power on reset or Hard Reset that holds the board including the configuration circuitry in reset until all power supplies on the board are within their tolerances The second reset circuit is the user reset or Soft reset 10 1 Power Reset The power reset signal holds the configuration circuit...

Page 101: ...PGAs When reset is triggered it remains triggered until 55us after all trigger conditions are removed This behavior prevents USB from behaving in such a way to permanently disable USB on the host machine Under some conditions the DN9002K10PCI can fail to be responsive after rapidly asserting and de asserting reset or if the board is powered off and back on very quickly This behavior is caused due ...

Page 102: ...onous reset and distribute this signal using a MB signal 11JTAG There are two JTAG headers on the DN9002K10PCI The first is used only to update the board s firmware The second J1 is connected to the JTAG port of the Virtex 5 FPGAs This interface can be used for configuring the FPGAs or using debugging tools like ChipScope or Identify 11 1 FPGA JTAG The connector for FPGA JTAG is shown below FPGA_T...

Page 103: ...AG 11 2 Firmware Update Header The firmware update JTAG header J16 should not be used unless you are updating the DN9002K10PCI firmware This header is used with a Xilinx Platform USB or Parallel IV cable The instructions for updating the firmware are in the Controller software chapter 11 3 Troubleshooting If you are having problems getting JTAG to work try connecting the Xilinx Platform USB cable ...

Page 104: ...ependent on the UART in the FPGA Since the flow control signals on the serial cable are not connected to the FPGA you cannot use hardware handshaking The other port settings parity stop bits speed and data bits are user design dependent 12 1 1 Configuration RS232 A second RS232 header P3 is for the configuration circuitry to give feedback to the user It is described in the section Configuration Se...

Page 105: ... THE THRESHOLD TEMPERATURE TEMPERATURE ALERT FPGA A CURRENT TEMPERATURE 79 DEGREES C THRESHOLD TEMPERATURE 80 DEGREES C THE FPGA HAS DROPPED BELOW THE ALARM THRESHOLD AND MAY NOW BE RECONFIGURED The FPGA can safely operate as hot as 120 degrees but timing is not guaranteed You can use the temperature setting in the ISE place and route tool to make timing allowances for operating the FPGA out of ra...

Page 106: ...ding into the FPGA To disable this behavior you must disable sanity check Adding the following line to your main txt file can do this Sanity check n Also when using encryption you must be careful to correctly set the startup clock option correctly in bitgen or the FPGA will fail to configure Whatever you do if you love your FPGAs do not disable the CRC Check option in bitgen They should have calle...

Page 107: ... all other signals on the bank are using the LVCMOS25 standard and then use the LVCMOS25 standard for the LED on that bank Do not use DCI on LED signals You can control the brightness of LEDs by either using a low drive setting DRIVE 2ma in the ucf file or by rapidly toggling the LED signal high and low LED Reference LED Signal Name The LED indicates the following when ON Designator Color DS19 42 ...

Page 108: ...DS11 GREEN ETH_LINK100 Ethernet PHY has established link 100Base 15 4 Power LEDs These LEDs indicate is one or more power supplies fail either outputting a voltage that is too high or too low The voltage that the LED indicates is marked in silkscreen near the LED LED Reference LED Signal Name The LED indicates the following when ON Designator Color DS6 DS5 RED POWER_FAIL One of the 1 0V power supp...

Page 109: ...socket interfaces on the DN9002K10PCI By convention the name of this interface is DIMMB In this section the interfaces may be called DIMM SODIMM or DDR2 interface interchangeably Signal names given in this section and in other documentation ucf files are given in the form DIMMB_ signal name 16 1 Power Each DDR2 SODIMM is capable of drawing 5A of current when in auto precharge mode The DN9002K10PCI...

Page 110: ...board 1 8V power supply When the DN9002K10PCI is shipped a jumper is installed connecting the DIMM FPGA Bank power to the 1 8V power rail Next to each of these jumpers is a 2 5V test point suitable for jumper ing to the DIMM power rail if necessary Some Dini Group products DNSODM_SDR DNSODM_DDR1 require this jumper to be installed When installing this jumper remove the 1 8V jumper to prevent short...

Page 111: ...bal clock GC pin on the Virtex 4 device To receive the signal use an LVDS_EXT input with DIFF_TERM attribute set to TRUE The CK0 CK1 and CK2 signals are length matched so this input should be synchronous to the clock input of the DIMM module The DQ and DM signals are synchronous to the DQS signals in each bank See the DDR2 SODIMM module specification for information on the timing of this interface...

Page 112: ...18_I_DCI standard The following signals are exceptions to this requirement On four of the DIMM interfaces external termination resistors are provided The signals with external termination are listed below DIMMB_A00 DIMMB_A01 DIMMB_A02 DIMMB_A03 DIMMB_A04 DIMMB_A05 DIMMB_A06 DIMMB_A07 DIMMB_A08 DIMMB_A09 DIMMB_A10 DIMMB_A11 DIMMB_A12 DIMMB_A13 DIMMB_A14 DIMMB_A15 DIMMB_CAS DIMMB_CS 0 DIMMB_ODT0 For...

Page 113: ...r control signals modules may be set into T2 mode In the reference design the modules are in T1 mode Address Control signals FPGA Assume a DCM in system synchronous mode Worst clock to out time of Virtex 5 3 37 with DCM No phase shift Worst setup time 0 097 Worst hold time 0 21 DIMM Setup 600ps Hold 600ps DQ signals DIMM DQS must be within 350ps of DQ DM setup 400ps Hold 400ps FPGA IDELAY setup 1 ...

Page 114: ...dules The interface implementation on these modules is not provided The customer must design the memory interface including timing and clocking 16 5 Test points Each DDR2 interface exposes five signals as test points located on the bottom of the PCB right under the SODIMM connector These signals are DQ0 DQS0p CK0p RAS and CAS The test points are labeled in silkscreen The test points near DIMMA imp...

Page 115: ... FPGAs are installed the interconnect available between FPGAs drops significantly In the Ordering Information chapter of this manual there is a block diagram showing the available features on a board loaded with LX220 or smaller FPGAs If the board has mixed LX220 and LX330 FPGAs then the interconnect available between any two FPGAs is the lesser of the signal counts shown in these diagrams Each FP...

Page 116: ...e DCM to use the optimal phase for transmit and receive clocks 250 MHz Use DDR clocking and DDR IO buffers 300 MHz Use source synchronous clocking between FPGAs The clock is driven with the data for each bus The receiving FPGA uses the clock signal received on a CC pin to clock the IOs in the bus An IDELAY element on the CC pin input delays the clock with respect to the data by a fixed amount to a...

Page 117: ...le 24mA 18 1 MB Signals The DN9002K10PCI in addition to the dense interconnect available between FPGAs in a point to point topology provides a 36 signal wide MB bus that is connected to both Virtex 5 FPGAs These signals are reserved 18 1 1 Disambiguation The MainBus has two meanings In this document it usually refers to the interface connecting the FPGAs to USB and PCI via the configuration circui...

Page 118: ...ve performance from FPGA to FPGA on this bus as high as 75Mhz if you adjust input and output clocks and perform a timing analysis Using LVCMOS25 with a drive strength of 24mA you can assume there is a 10ns rise time flight time for signals on this bus No length matching is done on the MB signals Virtex 5 clock to out time 3 37ns with DCM Virtex 5 setup time 0 97ns Flight time 10ns includes rise ti...

Page 119: ...e Spartan 3 FPGA when the reference design is in use All transfers a synchronous to the USB_CLK or SYS_CLK signal This clock is fixed at 48 MHz and cannot be changed by the user This clock is LVCMOS single ended When the configuration circuit asserts the ALE signal the slave device on the bus the FPGA is required to register the data on the AD bus This is the main bus address All future transfers ...

Page 120: ...it hexadecimal numbers 18 3 1 Conventional Memory map By convention FPGAs on the main bus interface are assigned address ranges Assigning address ranges is required because the FPGA sourced signals DONE need to be driven by only one FPGA at a time The convention that Dini Group uses is to reserve the upper four bits in the address as an FPGA select address The address range hex 0x00000000 0x0FFFFF...

Page 121: ...res Tri mode Mac controller http www opencores org projects cgi web ethernet_tri_mode overview 19 1 MII The 4 bit GMII interface is the only required interface on the PHY device The EEPROM MDIO and other signals are only required if you want to put the PHY into a mode that is not default The SMI MDC MDIO signals address is set to 0000 Each Ethernet interface one for FPGA D one for F is on its own ...

Page 122: ...ice to be based on a clock that is delayed 2ns from the clock on the external TX_CLK and RX_CLK pins This makes synchronous operation of the interface possible Length Matched 500ps FPGA Assume a DCM in system synchronous mode Worst clock to out time of Virtex 5 3 37 with DCM No phase shift Worst setup time 0 097 Worst hold time 0 21 PHY clock measured at PHY pin clock out 2ns setup 2ns valid 1 2ns...

Page 123: ...n weekends and vacations If you do not implement the MDIO interface then the default settings are used for the device This includes settings that are specified by multi level inputs connected to resistors The CMODE options of the Ethernet PHYs has been set as follows CMODE0 0100 8 25K resistor CMODE1 0000 0 Ohm resistor CMODE2 0001 2 2K resistor CMODE3 0000 0 Ohm resistor This results in the follo...

Page 124: ... located next to the RJ45 connector indicates link in 100Mbit mode The 10Mb link LED is not configured Hot plug is acceptable on a 1000Base T connection The Ethernet PHY works with the Xilinx Ethernet IP but only in 10 and 100Mbit modes The above schematic clipping is useless but looks cool and technological 19 2 JTAG The VSC8601 device is attached to a JTAG chain The schematic clipping showing th...

Page 125: ...n be used for any user defined purpose requiring static memory intensive tasks like remembering your name and birthday The interface to the EPROM is a standard IIC at 1 8V The IIC address of the devices is binary 1010 000 The maximum clock speed of the IIC interface is 400 kHz ETH_TDO ETH_TDI R223 4 7K R206 4 7K R220 4 7K ETH_TCK R202 4 7K 3 3V R211 4 7K ETH_TMS ETH_TRST J4 TENTH1X6 1 2 3 4 5 6 1 ...

Page 126: ...s place and route within your design and are more flexible than a stand alone analyzer 21 1 FPGA B Mictor J16 is a Mictor connector whose signals all connect directly to FPGA B s IOs This Mictor can be used for a logic analyzer as probe points using a Mictor breakout or to cable to another system By default the signaling level on the Mictor connector is CMOS 2 5V Removing R134 and installing a zer...

Page 127: ...12 14 16 18 20 22 24 26 28 30 32 34 36 38 GND GND GND GND GND LOC MICTOR_B16 MICTOR_B32 MICTOR_B4 MICTOR_B8 SM MICTOR_B14 MICTOR_B23 MICTOR_B15 MICTOR_B29 MICTOR_B10 Hot plugging a Mictor connector is generally safe When connected to a logic analyzer signals MICTOR32 and MICTOR33 should be used as trigger signals Signals connected to the Mictor are 50 ohm DCI and SSTL referenced input can be used ...

Page 128: ...t that possibility 22Power The power used by the DN9002K10PCI is derived from external 5 0V and 3 3V voltage supplies The current at these voltages is supplied through the ATX power connector P2 or the PCI edge connector The maximum power draws on each of these rails is given below SELECTMAP_D7 GND CLK D15 D0 CLK D0 D15 Do Not Connect 2 767004 2 CONN_MICTOR38 1 3 5 7 9 11 13 15 17 19 21 23 25 27 2...

Page 129: ...n provided Therefore the user must limit the power dissipated by his design More typically each FPGA would only use 10A and daughtercards would use little or no power on 5 0V Under these conditions the 5 0V power requirement is only 4A 20W 22 2 3 3V 3 3V is used by the DN9002K10PCI to supply the clock distribution network the configuration logic Micro controller and Spartan 3 FPGA and daughtercard...

Page 130: ...D 5 GND 5 GND PWROK 5VSB 12 3 3 12 GND PSON GND GND GND 5 5 5 MTH1 MTH2 3 3V 3 3V 5 0V This connector will work with a standard ATX power supply Any supply rated above 300W is likely to be suitable for use with the DN9002K10PCI Some budget power supplies do not regulate 5 0V to within the margin required by the DN9002K10PCI If the 5 0V power rail drops below 4 6V then the DN9002K10PCI will automat...

Page 131: ...sure that the 5V and 3 3V rails supplied by the aux power connector are on the same regulated rail as the ones on the PCI power connector or risk back powering the host computer Do not back power the host 22 7 Power Monitors The DN9002K10PCI monitors the voltage levels on the board to ensure they are within tolerance If they fall out of tolerance above or below voltage the board will enter a reset...

Page 132: ...ount your design uses Put this number in the settings of the timing analyzer Power requirements of a design can be estimated using the power estimator tool in ISE 9 1 For this calculation the board is assumed to be in an ambient temperature of 35 degrees In a closed computer case the ambient temperature will increase 22 8 1 Fans The fan units attached above the heat sinks are powered by 5V Each fa...

Page 133: ...tors on the DN9002K10PCI Items considered test points including the clock TP points are listed in the test point section 23 1 FPGA User Interface Connectors The following connectors are directly connected to the FPGA and the user needs to know the interface requirements in detail All of these connectors should be fully described in the manual section indicated below FPGA Interface Connectors Refer...

Page 134: ... directly connected to FPGA IO and therefore the user does not need to know detailed information about them The interfaces relating to these connectors are functionally described in the manual section indicated The FPGA indicated is used to access the connector s interface but is not directly connected to the connector pins Non User connectors Reference Manufacturer Part Number Connector descripti...

Page 135: ...se Connectors Reference Manufacturer Part Number Connector description Y5 Gompf 93340115 PCI Bracket JP1 NONE NONE 1 8V adjust 1 8V adjust TP12 Mill Max 999 11 210 10 0 Jumper 1 8V connects to DIMMS X1 AMP Tyco 2 641260 1 8 pin DIP socket Used by the DN9002K10PCI to store firmware data MP2 CCI B 250 6 1 5 Board Stiffeners Board stiffeners MP1 CCI B 250 6 1 5 Board Stiffeners Board stiffeners M1 3 ...

Page 136: ...talled and the ATX power connector not connector is 30mm Lower profile fans are available 14mm but they may not have enough thermal performance for very power hungry designs Mounting holes are all over the place These are grounded Metal runners are along both edges of the board These are for ground oscilloscope probe ground clips You should also handle the DN9002K10PCI by its ground bars to help p...

Page 137: ...ly connectors Even though it uses the same FCI connector it is NOT compatible with the 300 pin MSA standard Each daughtercard connector provides 186 signals plus 4 clocks to its associated FPGA The signals can be used with just about any setting of IOSTANDARD and can be used differentially DN9002K10PCI User Guide www dinigroup com 127 ...

Page 138: ... connectors used in the expansion system are FCI MEG Array 400 pin plug 6mm part 84520 102 This connector is capable of as much as 10Gbs transmission rates using differential signaling All daughter card expansion headers on the DN9002K10PCI are located on the bottom side of the PWB This is done to eliminate the need for resolving board to board clearance issues assuming the daughter card uses no l...

Page 139: ...s from the top of the PCB looking through to the bottom side The Dini Group standard daughtercard DNMEG_OBS400 is compatible with the DN9002K10PCI The mounting holes are designed to be used with 14mm M3 standoffs Dini Group has available appropriate mounting hardware on request Standoffs Male to Female Part 1789 Harwin R30 3001402 DN9002K10PCI User Guide www dinigroup com 129 ...

Page 140: ... on the daughter card This dimension is determined by the daughter card designer s part selection for the MEG Array receptacle Note that the components on the topside of the daughter card and DN9002K10PCI face in opposite directions 25 1 2 Type 2 Short 400pin Short The daughtercard mechanical provisions on the DN9002K10PCI are for a type 2 short daughtercard The DNMEGOBS 400 is of these dimensions...

Page 141: ...nsertion and removal Due to the small dimensions of the very high speed Meg Array connector system the pins on the plug and receptacle of the Meg Array connectors are very delicate When plugging in a daughter card make sure to align the daughter card first before pressing on the connector Be absolutely certain that both the small and the large keys at the narrow ends of the Meg Array line up BEFOR...

Page 142: ... connector contacts Rough alignment of the connector is achieved through matching the Small alignment slot of the plug housing with the Small alignment key of the receptacle housing and the large alignment slot with the large alignment key Both connector housings have generous lead in around the perimeter and will allow the user to blind mate assemble the connectors Align the two connectors by fee...

Page 143: ...the DN9002K10PCI expansion system was designed to reduce cross talk to manageable levels while operating at full speed of the Virtex 5 The ground to signal ratio of the connector is 1 1 General purpose IO is arranged in a GSGS pattern to allow high speed single ended or differential use On the DN9002K10PCI host these signals are routed as loosely coupled differential signals meaning when used diff...

Page 144: ...ntain a _C in the pin name Pins declared in the above diagram that are underlined are connected to VREF pins on the Virtex 5 FPGA These FPGA pins are used to supply a voltage reference used as the threshold voltage for the signals on that bank The use of these pins is only necessary when using threshold standards such as SSTL DCI is used on all FPGA IO banks connected to a daughter card header The...

Page 145: ... daughtercard adding 0 5ns delay to account for the trace delay on the DN9002K10PCI The host FPGA will use a DCM in zero delay mode and the logic on the daughtercard should a low clock to out and setup times or use a DCM This method has the disadvantage of only allowing the one FPGA attached to the daughtercard to use this frequency To communicate globally across the DN9002K10PCI the user would ha...

Page 146: ...m the two 12V pins for a total of 24W Each power rail supplied to the Daughter card is fused with a reset able switch Daughter cards are required to provide their own power supply bypassing and onrus current limiting It is also asserted when the User Reset is active When RSTn is de asserted the 3 3V 5 0V and 12V power rails are guaranteed to be within the DN9002K10PCI tolerance If there are additi...

Page 147: ...his does not require modification of the DN9002K10PCI 25 3 Rolling your own daughtercard Small quantities of the connectors requ If you need help designing a daughtercard we will be happy to review your schematic for errors Send it 26Troubleshooting If the board is not responding at all w power failure LEDs If any of th problem If the failing voltage is 3 3V 5V or 12V then the problem is probably ...

Page 148: ...ng errors in the timing report SecureCRT program because it doesn t suck Hopefully the RS232 configuration status dump will tell you exactly what the problem is In any case the Dini Group will need this capture t diagnose the problem 26 2 The FPGAs won t program First connect the RS23 print an error message to this terminal Com report are The syntax in the main txt file is incorrect The bit fil If...

Page 149: ...o a pin and observe it 26 4 The DCMs won t lock reference clock input Check the follo DFS_FREQUENCY_MODE DFS_FREQUENCY_MODE 2 All clock inputs of the DCM are requi or another DCM you will need to build a delayed reset circuit to reset the second DCM 3 Make sure the global clock you are using is being received with an LVDS receiver not a is with high frequency clocks 26 5 The board resets to connec...

Page 150: ......

Page 151: ...AM Modules At 250Mhz Known good bitfiles for programming over USB PCI CompactFlash or JTAG RS232 Communication FPGA Interconnect using IO Flip flops FPGA Interconnect using advanced source synchronous techniques High Speed PCI DMA mode to FPGA A Main Bus interface for USB and PCI communication Main Bus memory mapping example to DDR2 block RAM Blink LEDs in cool patterns Reset Button New internal V...

Page 152: ...ming_Files DN9002K10PCI MainTest Four other self contained designs are on the CD and described in this manual These four designs are described in their own sections later in this chapter The remaining sections describe the MainTest design MainTest The reference design and The Dini Group reference design are the same thing The four additional designs are PCI Interface Design Tests the 64 bit interf...

Page 153: ... there may be multiple addresses on Main Bus that access the same registers Address Register Register Range Name Contents 0x00000000 DDR2 The data contained in the DDR2 SODIMM memory 0x07FFFFFF 0x08000001 DDR2HIADDR The upper bits of DDR2 address MainBus memory space is smaller than most DDR2 SODIMMs 0x08000002 IDCODE 0x05000142 0x08000003 DDR2HIADDRSIZE The number of valid addresses in DDR2HIADDR...

Page 154: ...lock 0x08000032 counters LVDS design only 0x08000033 MCLK_COUNTER Clock counters for in backwards order DDR2 clock 0x0800003F EXTCLK0 EXTCLK1 SMACLK CLK_FBE CLK_FBB CLK125_ETH CLKP CLK_TPp 0x08000040 DDR2TESTTAPCNT Reserved for manufacturing tests DDR2 0x08000043 0x08000044 LED_OE Controls LED output enables 0x08000045 LED_OUT Controls LED output values 0x08000046 DDR2SIZE_SODIMM2 Controls address...

Page 155: ...E register bank and an IN register bank The addresses of the IO registers are as follows FpgaNum 4 bit MB_SEL_INTERCON 4 bit busnum 20 bit reg_offset 4 bit FPGA NUM is 0x0 for FPGA A 0x1 for FPGA B 0x2 for FPGA C MB_SEL_INTERCON is 0xC busnum is any number but only low values less than LAST_ADDR will constrain valid busses reg_offset is 0x0 for REG_OUT 0x4 for REG_OE 0x8 for REG_IN and 0xC for REG...

Page 156: ...sents an FPGA ID as described in the MainBus interface description X are don t care Since the remaining 19 bits are insufficient to address an entire 4GB DRAM there is a register DDR2HIADDR that selects the highest address bits of the DRAM Each address refers to a 32 bit location in the DRAM The lowest bit is not mapped to DRAM address but instead selects between the upper and lower 32 bits of the...

Page 157: ...im_single v Source can be found on the user CD D FPGA_Reference_Designs DN9002K10PCI MainTest source Also you must add to the project a simulation library Simulation models of all of the primitives used in the reference design are found in the Xilinx ISE install directory in the unisims directory Simulation models are also provided of the DN9002K10PCI as a whole board along with DDR2 modules heade...

Page 158: ...ilinx bin directory to your path so the command par calls the correct program The build script creates a directory called out and places its output files there After the script completes you will find files for each FPGA that was built fpga_ bit is the file to be downloaded to the FPGA 8 2 Bitgen Options The Make bat script correctly sets all bitgen options that are compatible with the DN9002k10PC...

Page 159: ... source is located at D FPGA_Reference_Designs DN9002K10PCI MainRef Note that this is the same source as the Main Reference Design To compile the design for LVDS define statements in the Verilog code must be added or removed The make bat utility described in the compiling the reference design section automatically adds and removes these directives The pre compiled bitfiles for this design are loca...

Page 160: ...rence Design is an FPGA A only design that implements the QL_Interface_Module interface described the document D FPGA_Reference_Designs DN00k10PCI PCI_interface QL5064_Interface_Module pdf This design implements a PCI target access and DMA interface to a block ram inside FPGA A The source code is located on the CD at D FPGA_Reference_Designs DN9002K10PCI PCI_interface Blockram_Access_A source The ...

Page 161: ... product release cycle If your board will ship with CES parts the quote will state the Xilinx part number of each FPGA on your board indicating a CES revision It is important that the user knows that CES parts may have limitations that are not listed in the Virtex 5 datasheet To read about these limitations see the Xilinx website and search for Virtex 5 errata In general it is the responsibility o...

Page 162: ...MHz when using the attribute EN_SYN TRUE Clocks 1 Only BUFG and BUFGCE are supported The remaining global clock buffer primitives are not supported 0OSERDES 1 Optional inversion for the divided clock CLKDIV in the OSERDES is not supported Configuration 1 Configuration bitstream compression and fallback reconfiguration are not supported 2 3 Small FPGAs The DN9002K10PCI is optimized for two Xilinx V...

Page 163: ...ome unusable and the amount of interconnect between FPGA A and B is reduced from 696 signals to 378 signals The Ethernet PCI and DIMMs are not affected by FPGA selection Also you should analyze your design to determine if the internal resources available in the LX110 and LX220 are sufficient to meet your needs The FPGA selection guide from Xilinx is printed below DN9002K10PCI User Guide www dinigr...

Page 164: ...d grade parts this is noted in the advertisement and in this document Below is a list of all such interfaces 1 PCI Express Some interfaces may run at increased speeds above and beyond Dini Group s advertised performances when used with 2 or 3 speed grade parts Some performance numbers that are advertised by Xilinx are listed here These characterizations have not been performed on the DN9002K10PCI ...

Page 165: ...quires DNSODM200_SRAM Memory module for use in the 200 pin SODIMM sockets Standard memory configuration Two GS8320V32 memories 1M x 32 each Performance up to 175Mhz SDR Small EPROM DNSODM200_QDR QDR SRAM module compatible with the DDR2 SODIMM sockets Two times 32 bit wide Small EPROM DNSODM200_NOBL Cypress no bus latency SRAM 64 bit wide Compatible with 200 pin SODIMM sockets Ask for availability ...

Page 166: ... bridge is used to isolate the primary PCI bus from the three secondary PCI bus slots Since primary and secondary busses are electrically isolated a much cleaner electrical signaling environment exists and a single host slot can be expanded to contain up to three plug in PCI cards The primary PCI frequency can range from 0 to 66 66 MHz The secondary PCI frequency is configurable to be the primary ...

Page 167: ...DR2 Memory High speed serial interfaces SMA SATA SFP others DNMEG_OBS Adjustable voltage tenth inch pitch headers User LEDs Two Mictor 38 connectors SMA global clock inputs for host board 3 2 Compatible third party products The following products have been shown to work with the DN9002K10PCI Intel Entry Server board SE7230NH1 E http www intel com design servers boards se7230nh1 e index htm DN9002K...

Page 168: ...an ambient temperature range of 0 50 degrees C All components used on the DN9002K10PCI are guaranteed to operate within a temperature range of 0 80 degrees C measured on the device die 4 3 Export Control 4 3 1 Lead Free The DN9002K10PCI meets the requirements of EU Directive 2002 95 EC RoHS Specifically the DN9002K10PCI contains no homogeneous materials that a contains lead Pb in excess of 0 1 wei...

Page 169: ...ide www dinigroup com 159 4 3 3 Export control classification number ECCN EAR99 4 4 Mission Critical DN9002K10PCI and supporting hardware and software are not intended for use on human subjects that you like in life support mission critical systems or aviation ...

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