Dini Group DN9002K10PCI, User Manual

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H A R D W A R E
can use the CLK_ETH_RX to clock inputs using a BUFIO and clock CLK_ETH_TX on the
same clock as the rest of your transmit signals.
By default, the 8601’s internal clock compensation mode is enabled. This causes the timing of
the device to be based on a clock that is delayed 2ns from the clock on the external TX_CLK
and RX_CLK pins. This makes synchronous operation of the interface possible.
Length-Matched: 500ps
FPGA:
Assume a DCM in system-synchronous mode.
Worst clock-to-out time of Virtex 5: 3.37 (with DCM.) No phase-shift.
Worst setup time: 0.097
Worst hold time: 0.21
PHY: (clock measured at PHY pin)
clock-out 2ns
setup 2ns
valid: 1.2ns
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