Dini Group DN9002K10PCI, User Manual

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T H E R E F E R E N C E D E S I G N
5 Clock Counters
Each clock available to the FPGA is connected to a counter register, and the value of this
register is available on MainBus. In this way, the user can determine if each clock input is
working properly.
6 LEDs
All of the LEDs are connected to an output enable register. When the LEDs are not enabled,
the blink a pattern representing which FPGA the design is for. When enabled, each LED is
controlled by the LED value register.
7 Simulating the Reference Design
The simulation environment the Dini Group uses is ModelSim. A ModelSim project file is
provided, but it may not be compatible with your version of ModelSim. When you create a
ModelSim project, add only the top-level design file (sim_single.v).
Source can be found on the user CD:
D:\FPGA_Reference_Designs\DN9002K10PCI\MainTest\source\
Also, you must add to the project a simulation library. Simulation models of all of the primitives
used in the reference design are found in the Xilinx ISE install directory in the unisims directory.
Simulation models are also provided of the DN9002K10PCI as a whole board, along with
DDR2 modules, headers and the MainBus interface.
8 Compiling the Reference Design
The MainTest reference design (for which bit files are included on the user CD and the
provided CompactFlash card) can be found on the user CD here.
D:\FPGA_Reference_Designs\
\common\DDR2\controller_ver\*
\ddr2_to_mb\*
\DN9002K10PCI
\MainTest\source\*
The top module is
D:\FPGA_Reference_Designs\DN9002K10PCI\MainTest\source\fpga.v
This module includes all of the other required sources and expects the directory structure found
on the CD.
DN9002K10PCI User Guide www.dinigroup.com 147