Dini Group DN9002K10PCI, User Manual

Page: 70 / 169

H A R D W A R E
A diagram of the global clock network is shown above. Each of the eight clock outputs of the
clock network is distributed to both FPGAs.
4.3 G0, G1, G2 Clocks
The G0, G1 and G2 clocks are the primary clock resource for your FPGA design. Each of these
clocks can be set to a wide range of frequencies between 2 and 550 MHz.
On the schematic, these signals are named
CLK_G*_*p
where * is 0,1 or 2 and * is the name of the FPGA connected to that signal.
The possible source of G0 and G1 clock is either the ICS8442 frequency synthesizer or a “step
clock”. The “step clock” is driven by the configuration circuit and can be toggled over USB or
PCI by writing to the correct configuration register. 0xDF23[2], 0xDF23[1]. Before the
Synthesizer or step clock drives the network, the correct source setting must be made in the
GUI or in the main.txt file. By default the source is the synthesizer.
The syntax to set the clock source in the main.txt file is
(contact
support@dinigroup.com . This setting does not exist yet)
In USB Controller, from the settings menu, select DN9002K10PCI clock source settings
DN9002K10PCI User Guide www.dinigroup.com 60