Dini Group DN9002K10PCI, User Manual

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H A R D W A R E
In a synchronous system between two FPGAs and a DCM in zero-delay mode, the following
timing is possible.
Clock to Out 3.37 NS
Trace Delay 1.70 NS
Rise-time adjustment 0.30 NS
Clock skew 0.20 NS
duty cycle 0.05 NS
jitter 0.05 NS
setup time 1.00 NS
Min Period 6.67 NS
Max Frequency 0.15 GHZ
If LVDS is used, make sure to assign the DIFF_TERM attribute to the IBUFDS in the receiver
FPGA.
As the frequency of synchronous communication between FPGAs increases, the user must
implement more difficult techniques. As a general guide, these techniques are described below.
0 MHz
20
MHz The user should use the “Pack the IOBs” by using synthesis attributes. The
output delay for each output and setup time for each input is a known value.
100 MHz Use DCMs in each FPGA to eliminate the variation of clock network skew
internal to each FPGA. The clock must be free-running
150 MHz Use the phase-adjustment feature of the DCM to use the optimal phase for
transmit and receive clocks.
250 MHz Use DDR clocking, and DDR IO buffers
300 MHz Use source-synchronous clocking between FPGAs. The clock is driven with the
data for each bus. The receiving FPGA uses the clock signal, received on a
“CC” pin to clock the IOs in the bus. An IDELAY element on the CC pin
input delays the clock with respect to the data by a fixed amount to allow some
setup time.
550 MHz Use the Virtex 5 build in ISERDES and OSERDES modules.
600 MHz Use Virtex 5 PLL devices to reduce cycle-to-cycle jitter on the clocks.
700 MHz Individually de-skew each bit using IDELAY elements. Use a training pattern
or hard-code the correct delay values for each input.
800 MHz Use LVDS signal standard
900 MHz dynamically de-skew each bit to account for temperature and voltage variation
1+ GHz use error-correcting encoding.
Note that for speeds above 550Mhz, you must use the ISERDES and OSERDES modules,
adding latency to your interconnect. (At speeds greater than 500Mhz, there is more than one
clock-cycle of latency in board trace delay alone).
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