Dini Group DN9002K10PCI, User Manual

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H A R D W A R E
AM16
9 System Monitor/ADC
The new Virtex 5 feature System Monitor allows the FPGA to use some of its IO as analog-to-
digital inputs.
The voltage measurements at these inputs are referenced to the voltage on the pin VREFP. On
the DN9002K10PCI, this voltage is generated by a high-precision external voltage reference IC.
The primary ADC input is routed to a differential test point. There is one test point labeled
“ADC” for each FPGA.
Some of the auxiliary inputs to the ADC are routed to the Mictor connector on FPGA B. This
could be used for something I guess.
10 Reset
There are two reset circuits on the DN9002K10PCI. One is the power-on reset, or “Hard
Reset”, that holds the board, including the configuration circuitry in reset until all power supplies
on the board are within their tolerances. The second reset circuit is the user reset, or “Soft
reset”.
10.1 Power Reset
The power-reset signal holds the configuration circuit (including a micro controller and Spartan
3 FPGA) in reset. It also causes the FPGAs to become un-configured, and causes the RSTn
signal on the daughter cards to be asserted. When the board is “in reset”, the “Hard Reset”
LED, DS85, is lit red. It is located about an inch above the USB connector.
DN9002K10PCI User Guide www.dinigroup.com 90