Dini Group DN9002K10PCI, User Manual

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H A R D W A R E
DN9002K10PCI User Guide www.dinigroup.com 64
The inputs are AC-coupled. This limits the minimum possible frequency of the clock input to
around 4 kHz. If you require an external clock with a frequency lower than this, you should
modify the board by removing the 4.7uF resistors shown above and replacing them with 0-ohm
resistors. The maximum recommended swing on the differential inputs is 3.3V.
To connect a single-ended clock source, you can connect to one of the SMA connectors, and
leave the other unconnected.
4.5 PCI Clock
The PCI Clock (“CLKP” in the schematic) is included for the purpose of synchronizing the
interface between the QL5064 PCI bridge chip and the FPGA A. The use of this clock with
PCI is not described, because the Dini Group provides a module, QL5064_interface_module,
that implements the QL5064 connection.
The clock is a single-ended LVCMOS (3.3V) signals distributed to FPGA A, FPGA B, the
Spartan Configuration FPGA, and the QL5064. The frequency of the clock is fixed at 75Mhz.
This frequency is chosen because it maximizes the performance of the QL5064 chip.
To receive the chip on FPGA A or B, use a LVCMOS33 input. Although the clock is designed
to be used with the QL5064_interface_module module, it can be used by the user design as well.
Details about how to connect this clock to the QL5064 module are in the QL5064 module
documentation on the user CD. Before providing this clock signal to the module, you must pass
the signal through a DCM, and pass the CLK0 output of the DCM through a BUFG. The
output of this BUFG is connected to the module.
4.6 Non-Global Clocks
The following sections describe clocks that are not considered “global” because they do not
distribute to both FPGAs on the board. These clocks may be used for specific interfaces and
details on the clocking required for those interfaces are found in a different section in the
hardware chapter.
4.6.1 Clock TP
Each FPGA is connected to a two-pinned test point. This test point can be used to input a
differential clock from off-board. Each of these test points has a 0-Ohm jumper installed
shorting the negative and positive signals. To input or output differentially, you must remove
this resistor.
CLKP_Q (to QL5064) 3
CMOS 23R
ICS553
SOIC127P600-8N
1
8
7
4
3
2
6
5
VDD/2,3,5
OE
Q3
GND
Q1
Q0
Q2
ICLK
CLKP_B (to FPGA B) 3
+3.3V
CLKP_A (to FPGA A) 3
+3.3V
75Mhz
5032
1
2
4
3
OE
Gnd
Vcc
OUT
5
6
7
8
4
3
2
1
20R
CLKP_S (to config FPGA) 3