Dini Group DN9002K10PCI, User Manual

Page: 119 / 169

H A R D W A R E
0xBABABABA: <unknown. Contact support>
0x12345678: The Main Bus is disabled. This is the default state of the DN9002K10PCI when it
powers on. To set the DN9002K10PCI to enable, a configuration register must be written. This
behavior is intended to protect users who do not with to implement Main Bus interface, but
who wish to use the MB0-MB35 signals for their own purposes.
18.3 FPGA Interface
All memory-mapped transactions in the reference design occur over the MB bus. This 36-signal
bus connects to all Virtex 5 FPGAs and to the Spartan 3 configuration FPGA. The
Configuration circuit (Spartan 3) is the master of the bus. All access to the MB bus (reads and
writes) is initiated by the Spartan 3 FPGA when the reference design is in use.
All transfers a synchronous to the USB_CLK (or SYS_CLK) signal. This clock is fixed at 48
MHz, and cannot be changed by the user. This clock is LVCMOS, single-ended. When the
configuration circuit asserts the ALE signal, the slave device on the bus (the FPGA) is required
to register the data on the AD bus. This is the “main bus address”. All future transfers over the
main bus are said to be at this address, until a new address is latched. On a later clock cycle, the
master may assert the “RD” signal. Sometime after this, (within 256 clock cycles), the FPGA
should assert DONE for one clock cycle. On this cycle, the master (Spartan) will register the
data on the AD bus, and that will be the read data. If DONE is not asserted, then a timeout will
be recorded and the transaction cancelled.
Here is a write transaction:
DN9002K10PCI User Guide www.dinigroup.com 109