Dini Group DN9002K10PCI, User Manual

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H A R D W A R E
When User reset is asserted, the RSTn signal to each daughtercard is also asserted.
The rise time of the reset signal is fairly slow (10s of nanoseconds), and the delay within the
FPGA of the reset signal cause the actual de-assertion time of the logic within the FPGA to be
uncertain by as many as 20ns. (the timing of a synchronous reset within a single FPGA is
guaranteed) This means that if this signal is used to reset circuitry used for inter-FPGA
communication, care needs to be taken that a synchronous reset is not required for the multiple-
FPGA system to operate correctly. Alternately, you design can re-generate a synchronous reset
and distribute this signal using a MB* signal.
11 JTAG
There are two JTAG headers on the DN9002K10PCI. The first is used only to update the
board’s firmware. The second, J1 is connected to the JTAG port of the Virtex-5 FPGAs. This
interface can be used for configuring the FPGAs, or using debugging tools like ChipScope or
Identify.
11.1 FPGA JTAG
The connector for FPGA JTAG is shown below.
FPGA_TCK
FPGAA_TDI
+2.5V
J7
CON14A
87832-1420 2mm
1 2
3 4
5 6
7 8
9 10
11 12
13 14
FPGA_TMS
FPGAB_TDO
Note that the signal “TDO” on the header and in the schematic refers to the “TDO” port of
the FPGA, not the connector.
The order of the FPGA JTAG chain is FPGA A->FPGA B. There are no other components in
the chain. If you received your board with fewer than two FPGAs installed, then the chain will
be shorter.
DN9002K10PCI User Guide www.dinigroup.com 92