Document Number: 002-10635 Rev. *I
Page
282 of 325
S6J3310/20/30/40 Series
Page
Section
Change Results
174
9.Electric
Characteristics
9.1.4.1.Source
clock timing
Revised as below:
Error)
Notes:
− The maximum/minimum values have been standardized with the main clock and PLL clock in use.
− Jitter of source oscillator must be smaller than 300ppm.
Correct)
Notes:
− The maximum/minimum values have been standardized with the main clock and PLL clock in use.
− Jitter of source oscillator must be smaller than 300ppm.
− Enough evaluation and adjustment are recommended using oscillator on your system board.
177
9.Electric
Characteristics
9.1.4.3.Internal
clock timing
Revised as below:
Error)
- Note that Ta=125 condition is not supported in this product type.
When using SSCG_PLL output for these internal clock, the MAX value of frequency has the following restrictions.
‐
On the presumption that the modulation mode of SSCG_PLL is used with down spread,
the MAX value of the frequency is standardized.
‐
This means that MAX value of frequency is the maximum value when SSCG_PLL was modulated.
Correct)
- Note that Ta=125 condition is not supported in this product type.
When using SSCG_PLL output for these internal clock, the MAX value of frequency has the following restrictions.
‐
On the presumption that the modulation mode of SSCG_PLL is used with down spread,
the MAX value of the frequency is standardized.
‐
This means that MAX value of frequency is the maximum value when SSCG_PLL was modulated.
‐
"Unused" means a clock source which doesn’t have any supply destinations. Configure it as disable with performing
at the lower clock frequency than the described maximum.
179
9.Electric
Characteristics
9.1.4.3.internal
clock timing
Added Oscillation clock frequency as below:
Correct)
Internal Operation Clock Frequency
Main
Clock
PLL Clock
Multiplied by
1
Multiplied by
2
Multiplied by
15
Multiplied by
30
Multiplied by
40
Multiplied by
60
Oscillation
clock
frequency
[MHz]
4
2
4
8
…
60
120
160
240
8
4
8
16
…
120
240
16
8
16
32
…
240
